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1 | /* |
2 | * Muxing for Gumstix Pepper and AM335x-based boards | |
3 | * | |
4 | * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/ | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | #include <common.h> | |
9 | #include <asm/arch/sys_proto.h> | |
10 | #include <asm/arch/hardware.h> | |
11 | #include <asm/arch/mux.h> | |
12 | #include <asm/io.h> | |
13 | #include <i2c.h> | |
14 | #include "board.h" | |
15 | ||
16 | static struct module_pin_mux uart0_pin_mux[] = { | |
17 | {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ | |
18 | {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ | |
19 | {-1}, | |
20 | }; | |
21 | ||
22 | static struct module_pin_mux mmc0_pin_mux[] = { | |
23 | {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ | |
24 | {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ | |
25 | {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ | |
26 | {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ | |
27 | {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ | |
28 | {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ | |
29 | {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ | |
30 | {-1}, | |
31 | }; | |
32 | ||
33 | static struct module_pin_mux i2c0_pin_mux[] = { | |
34 | /* I2C_DATA */ | |
35 | {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, | |
36 | /* I2C_SCLK */ | |
37 | {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, | |
38 | {-1}, | |
39 | }; | |
40 | ||
41 | static struct module_pin_mux rgmii1_pin_mux[] = { | |
42 | {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ | |
43 | {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ | |
44 | {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ | |
45 | {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ | |
46 | {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ | |
47 | {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ | |
48 | {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ | |
49 | {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ | |
50 | {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ | |
51 | {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ | |
52 | {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ | |
53 | {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ | |
54 | {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ | |
55 | {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ | |
56 | {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */ | |
57 | {OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */ | |
58 | {OFFSET(xdma_event_intr1), MODE(3)}, | |
59 | {-1}, | |
60 | }; | |
61 | ||
62 | void enable_uart0_pin_mux(void) | |
63 | { | |
64 | configure_module_pin_mux(uart0_pin_mux); | |
65 | } | |
66 | ||
67 | /* | |
68 | * Do board-specific muxes. | |
69 | */ | |
70 | void enable_board_pin_mux(void) | |
71 | { | |
72 | /* I2C0 */ | |
73 | configure_module_pin_mux(i2c0_pin_mux); | |
74 | /* SD Card */ | |
75 | configure_module_pin_mux(mmc0_pin_mux); | |
76 | /* Ethernet pinmux. */ | |
77 | configure_module_pin_mux(rgmii1_pin_mux); | |
78 | } |