[people/ms/u-boot.git] / board / hidden_dragon / early_init.S

/*
 * (C) Copyright 2001
 * Thomas Koeller, tkoeller@gmx.net
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef	__ASSEMBLY__
#define __ASSEMBLY__	1
#endif

#include <config.h>
#include <asm/processor.h>
#include <mpc824x.h>
#include <ppc_asm.tmpl>

#if defined(USE_DINK32)
  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
  #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
#else
  #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
#endif

	.text

	/* Values to program into memory controller registers */
tbl:	.long	MCCR1, MCCR1VAL
	.long	MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
	.long	MCCR3
	.long	(((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT)
	.long	MCCR4
	.long	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
		(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
		(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
		((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
		(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
		(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
		((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
	.long	MSAR1
	.long	(((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
	.long	EMSAR1
	.long	(((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
	.long	MSAR2
	.long	(((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
	.long	EMSAR2
	.long	(((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
	.long	MEAR1
	.long	(((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
	.long	EMEAR1
	.long	(((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
	.long	MEAR2
	.long	(((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
	.long	EMEAR2
	.long	(((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
	.long	0


	/*
	 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
	 * must be done in assembly, since we have no stack at this point.
	 */
	.global	early_init_f
early_init_f:
	mflr	r10

	/* basic memory controller configuration */
	lis	r3, CONFIG_ADDR_HIGH
	lis	r4, CONFIG_DATA_HIGH
	bl	lab
lab:	mflr	r5
	lwzu	r0, tbl - lab(r5)
loop:	lwz	r1, 4(r5)
	stwbrx	r0, 0, r3
	eieio
	stwbrx	r1, 0, r4
	eieio
	lwzu	r0, 8(r5)
	cmpli	cr0, 0, r0, 0
	bne	cr0, loop

	/* set bank enable bits */
	lis	r0, MBER@h
	ori	r0, 0, MBER@l
	li	r1, CONFIG_SYS_BANK_ENABLE
	stwbrx	r0, 0, r3
	eieio
	stb	r1, 0(r4)
	eieio

	/* delay loop */
	lis	r0, 0x0003
	mtctr   r0
delay:	bdnz	delay

	/* enable memory controller */
	lis	r0, MCCR1@h
	ori	r0, 0, MCCR1@l
	stwbrx	r0, 0, r3
	eieio
	lwbrx	r0, 0, r4
	oris	r0, 0, MCCR1_MEMGO@h
	stwbrx	r0, 0, r4
	eieio

	/* set up stack pointer */
	lis	r1, CONFIG_SYS_INIT_SP_OFFSET@h
	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l

	mtlr	r10
	blr
Commit	Line	Data
756f586a WD	1	/*
	2	* (C) Copyright 2001
	3	* Thomas Koeller, tkoeller@gmx.net
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __ASSEMBLY__
	25	#define __ASSEMBLY__ 1
	26	#endif
	27
	28	#include <config.h>
	29	#include <asm/processor.h>
	30	#include <mpc824x.h>
	31	#include <ppc_asm.tmpl>
	32
	33	#if defined(USE_DINK32)
	34	/* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
6d0f6bcf	35	#define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) \| (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) \| MCCR1_MEMGO)
756f586a	36	#else
6d0f6bcf	37	#define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) \| (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
756f586a WD	38	#endif
	39
	40	.text
	41
	42	/* Values to program into memory controller registers */
	43	tbl: .long MCCR1, MCCR1VAL
6d0f6bcf	44	.long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
756f586a	45	.long MCCR3
6d0f6bcf JCPV	46	.long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) \| \
	47	(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) \| \
	48	(CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)
756f586a	49	.long MCCR4
6d0f6bcf JCPV	50	.long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \| (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \| \
	51	(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) \| \
	52	(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) \| \
	53	((CONFIG_SYS_SDMODE_CAS_LAT << 4) \| (CONFIG_SYS_SDMODE_WRAP << 3) \| \
	54	(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) \| \
	55	(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) \| \
	56	((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
756f586a	57	.long MSAR1
6d0f6bcf JCPV	58	.long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) \| \
	59	(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \| \
	60	(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \| \
	61	(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
756f586a	62	.long EMSAR1
6d0f6bcf JCPV	63	.long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) \| \
	64	(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \| \
	65	(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \| \
	66	(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
756f586a	67	.long MSAR2
6d0f6bcf JCPV	68	.long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) \| \
	69	(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \| \
	70	(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \| \
	71	(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
756f586a	72	.long EMSAR2
6d0f6bcf JCPV	73	.long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) \| \
	74	(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \| \
	75	(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \| \
	76	(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
756f586a	77	.long MEAR1
6d0f6bcf JCPV	78	.long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) \| \
	79	(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \| \
	80	(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \| \
	81	(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
756f586a	82	.long EMEAR1
6d0f6bcf JCPV	83	.long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) \| \
	84	(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \| \
	85	(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \| \
	86	(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
756f586a	87	.long MEAR2
6d0f6bcf JCPV	88	.long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) \| \
	89	(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \| \
	90	(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \| \
	91	(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
756f586a	92	.long EMEAR2
6d0f6bcf JCPV	93	.long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) \| \
	94	(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \| \
	95	(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \| \
	96	(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
756f586a WD	97	.long 0
	98
	99
	100	/*
	101	* Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
	102	* must be done in assembly, since we have no stack at this point.
	103	*/
	104	.global early_init_f
	105	early_init_f:
	106	mflr r10
	107
	108	/* basic memory controller configuration */
	109	lis r3, CONFIG_ADDR_HIGH
	110	lis r4, CONFIG_DATA_HIGH
	111	bl lab
	112	lab: mflr r5
	113	lwzu r0, tbl - lab(r5)
	114	loop: lwz r1, 4(r5)
	115	stwbrx r0, 0, r3
	116	eieio
	117	stwbrx r1, 0, r4
	118	eieio
	119	lwzu r0, 8(r5)
	120	cmpli cr0, 0, r0, 0
	121	bne cr0, loop
	122
	123	/* set bank enable bits */
	124	lis r0, MBER@h
	125	ori r0, 0, MBER@l
6d0f6bcf	126	li r1, CONFIG_SYS_BANK_ENABLE
756f586a WD	127	stwbrx r0, 0, r3
	128	eieio
	129	stb r1, 0(r4)
	130	eieio
	131
	132	/* delay loop */
	133	lis r0, 0x0003
	134	mtctr r0
	135	delay: bdnz delay
	136
	137	/* enable memory controller */
	138	lis r0, MCCR1@h
	139	ori r0, 0, MCCR1@l
	140	stwbrx r0, 0, r3
	141	eieio
	142	lwbrx r0, 0, r4
	143	oris r0, 0, MCCR1_MEMGO@h
	144	stwbrx r0, 0, r4
	145	eieio
	146
	147	/* set up stack pointer */
6d0f6bcf JCPV	148	lis r1, CONFIG_SYS_INIT_SP_OFFSET@h
6d0f6bcf JCPV	149	ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
756f586a WD	150
	151	mtlr r10
	152	blr