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37fc0ed2 RH |
1 | /* |
2 | * Copyright 2010-2011 Calxeda, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <common.h> | |
19 | #include <ahci.h> | |
bd0d90ef | 20 | #include <netdev.h> |
37fc0ed2 RH |
21 | #include <scsi.h> |
22 | ||
23 | #include <asm/sizes.h> | |
877012df | 24 | #include <asm/io.h> |
37fc0ed2 | 25 | |
0c34e69f | 26 | #define HB_SREG_A9_PWR_REQ 0xfff3cf00 |
4a3ea216 | 27 | #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 |
0c34e69f RH |
28 | #define HB_PWR_SUSPEND 0 |
29 | #define HB_PWR_SOFT_RESET 1 | |
30 | #define HB_PWR_HARD_RESET 2 | |
31 | #define HB_PWR_SHUTDOWN 3 | |
32 | ||
37fc0ed2 RH |
33 | DECLARE_GLOBAL_DATA_PTR; |
34 | ||
35 | /* | |
36 | * Miscellaneous platform dependent initialisations | |
37 | */ | |
38 | int board_init(void) | |
39 | { | |
40 | icache_enable(); | |
41 | ||
42 | return 0; | |
43 | } | |
44 | ||
9a420986 RH |
45 | /* We know all the init functions have been run now */ |
46 | int board_eth_init(bd_t *bis) | |
47 | { | |
48 | int rc = 0; | |
49 | ||
50 | #ifdef CONFIG_CALXEDA_XGMAC | |
51 | rc += calxedaxgmac_initialize(0, 0xfff50000); | |
52 | rc += calxedaxgmac_initialize(1, 0xfff51000); | |
53 | #endif | |
54 | return rc; | |
55 | } | |
56 | ||
37fc0ed2 RH |
57 | int misc_init_r(void) |
58 | { | |
4a3ea216 RH |
59 | char envbuffer[16]; |
60 | u32 boot_choice; | |
61 | ||
37fc0ed2 RH |
62 | ahci_init(0xffe08000); |
63 | scsi_scan(1); | |
4a3ea216 RH |
64 | |
65 | boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff; | |
66 | sprintf(envbuffer, "bootcmd%d", boot_choice); | |
67 | if (getenv(envbuffer)) { | |
68 | sprintf(envbuffer, "run bootcmd%d", boot_choice); | |
69 | setenv("bootcmd", envbuffer); | |
70 | } else | |
71 | setenv("bootcmd", ""); | |
72 | ||
37fc0ed2 RH |
73 | return 0; |
74 | } | |
75 | ||
76 | int dram_init(void) | |
77 | { | |
78 | gd->ram_size = SZ_512M; | |
79 | return 0; | |
80 | } | |
81 | ||
82 | void dram_init_banksize(void) | |
83 | { | |
84 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
85 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
86 | } | |
87 | ||
88 | void reset_cpu(ulong addr) | |
89 | { | |
0c34e69f | 90 | writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); |
5bedf884 RH |
91 | |
92 | wfi(); | |
37fc0ed2 | 93 | } |