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Commit | Line | Data |
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37fc0ed2 RH |
1 | /* |
2 | * Copyright 2010-2011 Calxeda, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
37fc0ed2 RH |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <ahci.h> | |
bd0d90ef | 9 | #include <netdev.h> |
37fc0ed2 RH |
10 | #include <scsi.h> |
11 | ||
1ace4022 | 12 | #include <linux/sizes.h> |
877012df | 13 | #include <asm/io.h> |
37fc0ed2 | 14 | |
76c3999d RH |
15 | #define HB_AHCI_BASE 0xffe08000 |
16 | ||
083ffd65 | 17 | #define HB_SCU_A9_PWR_STATUS 0xfff10008 |
0c34e69f | 18 | #define HB_SREG_A9_PWR_REQ 0xfff3cf00 |
4a3ea216 | 19 | #define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04 |
76c3999d | 20 | #define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20 |
f8973325 | 21 | #define HB_SREG_A15_PWR_CTRL 0xfff3c200 |
76c3999d | 22 | |
0c34e69f RH |
23 | #define HB_PWR_SUSPEND 0 |
24 | #define HB_PWR_SOFT_RESET 1 | |
25 | #define HB_PWR_HARD_RESET 2 | |
26 | #define HB_PWR_SHUTDOWN 3 | |
27 | ||
76c3999d RH |
28 | #define PWRDOM_STAT_SATA 0x80000000 |
29 | #define PWRDOM_STAT_PCI 0x40000000 | |
30 | #define PWRDOM_STAT_EMMC 0x20000000 | |
31 | ||
083ffd65 RH |
32 | #define HB_SCU_A9_PWR_NORMAL 0 |
33 | #define HB_SCU_A9_PWR_DORMANT 2 | |
34 | #define HB_SCU_A9_PWR_OFF 3 | |
35 | ||
37fc0ed2 RH |
36 | DECLARE_GLOBAL_DATA_PTR; |
37 | ||
38 | /* | |
39 | * Miscellaneous platform dependent initialisations | |
40 | */ | |
41 | int board_init(void) | |
42 | { | |
43 | icache_enable(); | |
44 | ||
45 | return 0; | |
46 | } | |
47 | ||
9a420986 RH |
48 | /* We know all the init functions have been run now */ |
49 | int board_eth_init(bd_t *bis) | |
50 | { | |
51 | int rc = 0; | |
52 | ||
53 | #ifdef CONFIG_CALXEDA_XGMAC | |
54 | rc += calxedaxgmac_initialize(0, 0xfff50000); | |
55 | rc += calxedaxgmac_initialize(1, 0xfff51000); | |
56 | #endif | |
57 | return rc; | |
58 | } | |
59 | ||
b9463226 IC |
60 | #ifdef CONFIG_SCSI_AHCI_PLAT |
61 | void scsi_init(void) | |
37fc0ed2 | 62 | { |
76c3999d | 63 | u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); |
4a3ea216 | 64 | |
76c3999d | 65 | if (reg & PWRDOM_STAT_SATA) { |
9efaca3e | 66 | ahci_init((void __iomem *)HB_AHCI_BASE); |
76c3999d RH |
67 | scsi_scan(1); |
68 | } | |
b9463226 IC |
69 | } |
70 | #endif | |
71 | ||
72 | #ifdef CONFIG_MISC_INIT_R | |
73 | int misc_init_r(void) | |
74 | { | |
75 | char envbuffer[16]; | |
76 | u32 boot_choice; | |
4a3ea216 RH |
77 | |
78 | boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff; | |
79 | sprintf(envbuffer, "bootcmd%d", boot_choice); | |
80 | if (getenv(envbuffer)) { | |
81 | sprintf(envbuffer, "run bootcmd%d", boot_choice); | |
82 | setenv("bootcmd", envbuffer); | |
83 | } else | |
84 | setenv("bootcmd", ""); | |
85 | ||
37fc0ed2 RH |
86 | return 0; |
87 | } | |
95395023 | 88 | #endif |
37fc0ed2 RH |
89 | |
90 | int dram_init(void) | |
91 | { | |
92 | gd->ram_size = SZ_512M; | |
93 | return 0; | |
94 | } | |
95 | ||
96 | void dram_init_banksize(void) | |
97 | { | |
98 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
99 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
100 | } | |
101 | ||
76c3999d | 102 | #if defined(CONFIG_OF_BOARD_SETUP) |
e895a4b0 | 103 | int ft_board_setup(void *fdt, bd_t *bd) |
76c3999d RH |
104 | { |
105 | static const char disabled[] = "disabled"; | |
106 | u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); | |
107 | ||
108 | if (!(reg & PWRDOM_STAT_SATA)) | |
109 | do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status", | |
110 | disabled, sizeof(disabled), 1); | |
111 | ||
112 | if (!(reg & PWRDOM_STAT_EMMC)) | |
113 | do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status", | |
114 | disabled, sizeof(disabled), 1); | |
e895a4b0 SG |
115 | |
116 | return 0; | |
76c3999d RH |
117 | } |
118 | #endif | |
119 | ||
f8973325 ML |
120 | static int is_highbank(void) |
121 | { | |
122 | uint32_t midr; | |
123 | ||
124 | asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); | |
125 | ||
126 | return (midr & 0xfff0) == 0xc090; | |
127 | } | |
128 | ||
37fc0ed2 RH |
129 | void reset_cpu(ulong addr) |
130 | { | |
0c34e69f | 131 | writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ); |
f8973325 ML |
132 | if (is_highbank()) |
133 | writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS); | |
134 | else | |
135 | writel(0x1, HB_SREG_A15_PWR_CTRL); | |
5bedf884 RH |
136 | |
137 | wfi(); | |
37fc0ed2 | 138 | } |