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a87589da | 1 | /* |
3515fd18 | 2 | * (C) Copyright 2003-2008 |
a87589da WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
8 | * (C) Copyright 2004 | |
9 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <common.h> | |
31 | #include <mpc5xxx.h> | |
32 | #include <pci.h> | |
3515fd18 | 33 | #include <asm/processor.h> |
6d51e505 | 34 | #include <malloc.h> |
a87589da WD |
35 | |
36 | #ifndef CFG_RAMBOOT | |
37 | static void sdram_start (int hi_addr) | |
38 | { | |
39 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
40 | ||
41 | /* unlock mode register */ | |
42 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; | |
43 | __asm__ volatile ("sync"); | |
44 | ||
45 | /* precharge all banks */ | |
46 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; | |
47 | __asm__ volatile ("sync"); | |
48 | ||
49 | #if SDRAM_DDR | |
50 | /* set mode register: extended mode */ | |
51 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; | |
52 | __asm__ volatile ("sync"); | |
53 | ||
54 | /* set mode register: reset DLL */ | |
55 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; | |
56 | __asm__ volatile ("sync"); | |
57 | #endif | |
58 | ||
59 | /* precharge all banks */ | |
60 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; | |
61 | __asm__ volatile ("sync"); | |
62 | ||
63 | /* auto refresh */ | |
64 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; | |
65 | __asm__ volatile ("sync"); | |
66 | ||
67 | /* set mode register */ | |
68 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; | |
69 | __asm__ volatile ("sync"); | |
70 | ||
71 | /* normal operation */ | |
72 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; | |
73 | __asm__ volatile ("sync"); | |
74 | } | |
75 | #endif | |
76 | ||
77 | /* | |
78 | * ATTENTION: Although partially referenced initdram does NOT make real use | |
79 | * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE | |
80 | * is something else than 0x00000000. | |
81 | */ | |
82 | ||
9973e3c6 | 83 | phys_size_t initdram (int board_type) |
a87589da WD |
84 | { |
85 | ulong dramsize = 0; | |
86 | #ifndef CFG_RAMBOOT | |
87 | ulong test1, test2; | |
3515fd18 | 88 | uint svr, pvr; |
a87589da WD |
89 | |
90 | /* setup SDRAM chip selects */ | |
91 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ | |
92 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ | |
93 | __asm__ volatile ("sync"); | |
94 | ||
95 | /* setup config registers */ | |
96 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; | |
97 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; | |
98 | __asm__ volatile ("sync"); | |
99 | ||
100 | #if SDRAM_DDR | |
101 | /* set tap delay */ | |
102 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; | |
103 | __asm__ volatile ("sync"); | |
104 | #endif | |
105 | ||
106 | /* find RAM size using SDRAM CS0 only */ | |
107 | sdram_start(0); | |
8d7e2732 | 108 | test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); |
a87589da | 109 | sdram_start(1); |
8d7e2732 | 110 | test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); |
a87589da WD |
111 | if (test1 > test2) { |
112 | sdram_start(0); | |
113 | dramsize = test1; | |
114 | } else { | |
115 | dramsize = test2; | |
116 | } | |
117 | ||
118 | /* memory smaller than 1MB is impossible */ | |
119 | if (dramsize < (1 << 20)) { | |
120 | dramsize = 0; | |
121 | } | |
122 | ||
123 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
124 | if (dramsize > 0) { | |
125 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + | |
126 | __builtin_ffs(dramsize >> 20) - 1; | |
127 | } else { | |
128 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ | |
129 | } | |
130 | ||
131 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ | |
132 | #else /* CFG_RAMBOOT */ | |
133 | ||
134 | /* retrieve size of memory connected to SDRAM CS0 */ | |
135 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; | |
136 | if (dramsize >= 0x13) { | |
137 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
138 | } else { | |
139 | dramsize = 0; | |
140 | } | |
141 | ||
142 | /* retrieve size of memory connected to SDRAM CS1 */ | |
143 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; | |
144 | if (dramsize2 >= 0x13) { | |
145 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | |
146 | } else { | |
147 | dramsize2 = 0; | |
148 | } | |
149 | ||
150 | #endif /* CFG_RAMBOOT */ | |
151 | ||
c6dc21c8 WD |
152 | /* |
153 | * On MPC5200B we need to set the special configuration delay in the | |
154 | * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM | |
155 | * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: | |
156 | * | |
157 | * "The SDelay should be written to a value of 0x00000004. It is | |
158 | * required to account for changes caused by normal wafer processing | |
159 | * parameters." | |
160 | */ | |
161 | svr = get_svr(); | |
162 | pvr = get_pvr(); | |
163 | if ((SVR_MJREV(svr) >= 2) && | |
164 | (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { | |
165 | ||
166 | *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; | |
167 | __asm__ volatile ("sync"); | |
168 | } | |
169 | ||
a87589da WD |
170 | /* return dramsize + dramsize2; */ |
171 | return dramsize; | |
172 | } | |
173 | ||
174 | int checkboard (void) | |
175 | { | |
176 | puts ("Board: HMI1001\n"); | |
177 | return 0; | |
178 | } | |
179 | ||
9f96ae44 WD |
180 | #ifdef CONFIG_PREBOOT |
181 | ||
182 | static uchar kbd_magic_prefix[] = "key_magic"; | |
183 | static uchar kbd_command_prefix[] = "key_cmd"; | |
184 | ||
185 | #define S1_ROT 0xf0 | |
186 | #define S2_Q 0x40 | |
187 | #define S2_M 0x20 | |
188 | ||
189 | struct kbd_data_t { | |
190 | char s1; | |
191 | char s2; | |
192 | }; | |
193 | ||
194 | struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) | |
195 | { | |
196 | kbd_data->s1 = *((volatile uchar*)(CFG_STATUS1_BASE)); | |
197 | kbd_data->s2 = *((volatile uchar*)(CFG_STATUS2_BASE)); | |
198 | ||
199 | return kbd_data; | |
200 | } | |
201 | ||
8d7e2732 | 202 | static int compare_magic (const struct kbd_data_t *kbd_data, char *str) |
9f96ae44 WD |
203 | { |
204 | char s1 = str[0]; | |
205 | char s2; | |
206 | ||
207 | if (s1 >= '0' && s1 <= '9') | |
208 | s1 -= '0'; | |
209 | else if (s1 >= 'a' && s1 <= 'f') | |
210 | s1 = s1 - 'a' + 10; | |
211 | else if (s1 >= 'A' && s1 <= 'F') | |
212 | s1 = s1 - 'A' + 10; | |
213 | else | |
214 | return -1; | |
215 | ||
216 | if (((S1_ROT & kbd_data->s1) >> 4) != s1) | |
217 | return -1; | |
218 | ||
219 | s2 = (S2_Q | S2_M) & kbd_data->s2; | |
220 | ||
221 | switch (str[1]) { | |
222 | case 'q': | |
223 | case 'Q': | |
224 | if (s2 == S2_Q) | |
225 | return -1; | |
226 | break; | |
227 | case 'm': | |
228 | case 'M': | |
229 | if (s2 == S2_M) | |
230 | return -1; | |
231 | break; | |
232 | case '\0': | |
233 | if (s2 == (S2_Q | S2_M)) | |
234 | return 0; | |
235 | default: | |
236 | return -1; | |
237 | } | |
238 | ||
239 | if (str[2]) | |
240 | return -1; | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
8d7e2732 | 245 | static char *key_match (const struct kbd_data_t *kbd_data) |
9f96ae44 | 246 | { |
8d7e2732 WD |
247 | char magic[sizeof (kbd_magic_prefix) + 1]; |
248 | char *suffix; | |
249 | char *kbd_magic_keys; | |
9f96ae44 WD |
250 | |
251 | /* | |
252 | * The following string defines the characters that can be appended | |
253 | * to "key_magic" to form the names of environment variables that | |
254 | * hold "magic" key codes, i. e. such key codes that can cause | |
255 | * pre-boot actions. If the string is empty (""), then only | |
256 | * "key_magic" is checked (old behaviour); the string "125" causes | |
257 | * checks for "key_magic1", "key_magic2" and "key_magic5", etc. | |
258 | */ | |
259 | if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) | |
260 | kbd_magic_keys = ""; | |
261 | ||
262 | /* loop over all magic keys; | |
263 | * use '\0' suffix in case of empty string | |
264 | */ | |
265 | for (suffix = kbd_magic_keys; *suffix || | |
266 | suffix == kbd_magic_keys; ++suffix) { | |
267 | sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); | |
268 | ||
269 | if (compare_magic(kbd_data, getenv(magic)) == 0) { | |
8d7e2732 | 270 | char cmd_name[sizeof (kbd_command_prefix) + 1]; |
9f96ae44 WD |
271 | char *cmd; |
272 | ||
273 | sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); | |
274 | cmd = getenv (cmd_name); | |
275 | ||
276 | return (cmd); | |
277 | } | |
278 | } | |
279 | ||
280 | return (NULL); | |
281 | } | |
282 | ||
283 | #endif /* CONFIG_PREBOOT */ | |
284 | ||
9f96ae44 WD |
285 | int misc_init_r (void) |
286 | { | |
287 | #ifdef CONFIG_PREBOOT | |
288 | struct kbd_data_t kbd_data; | |
289 | /* Decode keys */ | |
8d7e2732 | 290 | char *str = strdup (key_match (get_keys (&kbd_data))); |
9f96ae44 WD |
291 | /* Set or delete definition */ |
292 | setenv ("preboot", str); | |
293 | free (str); | |
294 | #endif /* CONFIG_PREBOOT */ | |
295 | ||
a87589da WD |
296 | return 0; |
297 | } | |
298 | ||
299 | int board_early_init_r (void) | |
300 | { | |
301 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ | |
302 | *(vu_long *)MPC5XXX_BOOTCS_START = | |
303 | *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); | |
304 | *(vu_long *)MPC5XXX_BOOTCS_STOP = | |
305 | *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); | |
306 | return 0; | |
307 | } | |
98128f38 WD |
308 | #ifdef CONFIG_PCI |
309 | static struct pci_controller hose; | |
310 | ||
311 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
312 | ||
313 | void pci_init_board(void) | |
314 | { | |
315 | pci_mpc5xxx_init(&hose); | |
316 | } | |
317 | #endif |