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Move bootretry code into bootretry.c and clean up
[people/ms/u-boot.git] / board / hymod / hymod.c
CommitLineData
16f21704
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
16f21704 6 *
6dd652fa 7 * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
16f21704
WD		 8 */
9
10#include <common.h>
0098e179 11#include <bootretry.h>
18d66533 12#include <cli.h>
16f21704 13#include <mpc8260.h>
6dd652fa 14#include <mpc8260_irq.h>
16f21704
WD		 15#include <ioports.h>
16#include <i2c.h>
17#include <asm/iopin_8260.h>
18
d87080b7
WD		 19DECLARE_GLOBAL_DATA_PTR;
20
16f21704
WD		 21/* ------------------------------------------------------------------------- */
22
23/* imports from eeprom.c */
6dd652fa
WD		 24extern int hymod_eeprom_read (int, hymod_eeprom_t *);
25extern void hymod_eeprom_print (hymod_eeprom_t *);
16f21704 26
6dd652fa
WD		 27/* imports from env.c */
28extern void hymod_check_env (void);
16f21704
WD		 29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * I/O Port configuration table
34 *
35 * if conf is 1, then that port pin will be configured at boot time
36 * according to the five values podr/pdir/ppar/psor/pdat for that entry
37 */
38
39const iop_conf_t iop_conf_tab[4][32] = {
40
41 /* Port A configuration */
6dd652fa
WD		 42 {
43 /* cnf par sor dir odr dat */
44 { 1, 1, 1, 0, 0, 0 }, /* PA31: FCC1 MII COL */
45 { 1, 1, 1, 0, 0, 0 }, /* PA30: FCC1 MII CRS */
46 { 1, 1, 1, 1, 0, 0 }, /* PA29: FCC1 MII TX_ER */
47 { 1, 1, 1, 1, 0, 0 }, /* PA28: FCC1 MII TX_EN */
48 { 1, 1, 1, 0, 0, 0 }, /* PA27: FCC1 MII RX_DV */
49 { 1, 1, 1, 0, 0, 0 }, /* PA26: FCC1 MII RX_ER */
50 { 1, 0, 0, 1, 0, 0 }, /* PA25: FCC2 MII MDIO */
51 { 1, 0, 0, 1, 0, 0 }, /* PA24: FCC2 MII MDC */
52 { 1, 0, 0, 1, 0, 0 }, /* PA23: FCC3 MII MDIO */
53 { 1, 0, 0, 1, 0, 0 }, /* PA22: FCC3 MII MDC */
54 { 1, 1, 0, 1, 0, 0 }, /* PA21: FCC1 MII TxD[3] */
55 { 1, 1, 0, 1, 0, 0 }, /* PA20: FCC1 MII TxD[2] */
56 { 1, 1, 0, 1, 0, 0 }, /* PA19: FCC1 MII TxD[1] */
57 { 1, 1, 0, 1, 0, 0 }, /* PA18: FCC1 MII TxD[0] */
58 { 1, 1, 0, 0, 0, 0 }, /* PA17: FCC1 MII RxD[3] */
59 { 1, 1, 0, 0, 0, 0 }, /* PA16: FCC1 MII RxD[2] */
60 { 1, 1, 0, 0, 0, 0 }, /* PA15: FCC1 MII RxD[1] */
61 { 1, 1, 0, 0, 0, 0 }, /* PA14: FCC1 MII RxD[0] */
62 { 1, 0, 0, 1, 0, 0 }, /* PA13: FCC1 MII MDIO */
63 { 1, 0, 0, 1, 0, 0 }, /* PA12: FCC1 MII MDC */
64 { 1, 0, 0, 1, 0, 0 }, /* PA11: SEL_CD */
65 { 1, 0, 0, 0, 0, 0 }, /* PA10: FLASH STS1 */
66 { 1, 0, 0, 0, 0, 0 }, /* PA09: FLASH STS0 */
67 { 1, 0, 0, 0, 0, 0 }, /* PA08: FLASH ~PE */
68 { 1, 0, 0, 0, 0, 0 }, /* PA07: WATCH ~HRESET */
69 { 1, 0, 0, 0, 1, 0 }, /* PA06: VC DONE */
70 { 1, 0, 0, 1, 1, 0 }, /* PA05: VC INIT */
71 { 1, 0, 0, 1, 0, 0 }, /* PA04: VC ~PROG */
72 { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */
73 { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */
74 { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */
53677ef1 75 { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */
6dd652fa 76 },
16f21704
WD		 77
78 /* Port B configuration */
6dd652fa
WD		 79 {
80 /* cnf par sor dir odr dat */
81 { 1, 1, 0, 1, 0, 0 }, /* PB31: FCC2 MII TX_ER */
82 { 1, 1, 0, 0, 0, 0 }, /* PB30: FCC2 MII RX_DV */
83 { 1, 1, 1, 1, 0, 0 }, /* PB29: FCC2 MII TX_EN */
84 { 1, 1, 0, 0, 0, 0 }, /* PB28: FCC2 MII RX_ER */
85 { 1, 1, 0, 0, 0, 0 }, /* PB27: FCC2 MII COL */
86 { 1, 1, 0, 0, 0, 0 }, /* PB26: FCC2 MII CRS */
87 { 1, 1, 0, 1, 0, 0 }, /* PB25: FCC2 MII TxD[3] */
88 { 1, 1, 0, 1, 0, 0 }, /* PB24: FCC2 MII TxD[2] */
89 { 1, 1, 0, 1, 0, 0 }, /* PB23: FCC2 MII TxD[1] */
90 { 1, 1, 0, 1, 0, 0 }, /* PB22: FCC2 MII TxD[0] */
91 { 1, 1, 0, 0, 0, 0 }, /* PB21: FCC2 MII RxD[0] */
92 { 1, 1, 0, 0, 0, 0 }, /* PB20: FCC2 MII RxD[1] */
93 { 1, 1, 0, 0, 0, 0 }, /* PB19: FCC2 MII RxD[2] */
94 { 1, 1, 0, 0, 0, 0 }, /* PB18: FCC2 MII RxD[3] */
95 { 1, 1, 0, 0, 0, 0 }, /* PB17: FCC3 MII RX_DV */
96 { 1, 1, 0, 0, 0, 0 }, /* PB16: FCC3 MII RX_ER */
97 { 1, 1, 0, 1, 0, 0 }, /* PB15: FCC3 MII TX_ER */
98 { 1, 1, 0, 1, 0, 0 }, /* PB14: FCC3 MII TX_EN */
99 { 1, 1, 0, 0, 0, 0 }, /* PB13: FCC3 MII COL */
100 { 1, 1, 0, 0, 0, 0 }, /* PB12: FCC3 MII CRS */
101 { 1, 1, 0, 0, 0, 0 }, /* PB11: FCC3 MII RxD[3] */
102 { 1, 1, 0, 0, 0, 0 }, /* PB10: FCC3 MII RxD[2] */
103 { 1, 1, 0, 0, 0, 0 }, /* PB09: FCC3 MII RxD[1] */
104 { 1, 1, 0, 0, 0, 0 }, /* PB08: FCC3 MII RxD[0] */
105 { 1, 1, 0, 1, 0, 0 }, /* PB07: FCC3 MII TxD[3] */
106 { 1, 1, 0, 1, 0, 0 }, /* PB06: FCC3 MII TxD[2] */
107 { 1, 1, 0, 1, 0, 0 }, /* PB05: FCC3 MII TxD[1] */
108 { 1, 1, 0, 1, 0, 0 }, /* PB04: FCC3 MII TxD[0] */
109 { 0, 0, 0, 0, 0, 0 }, /* PB03: pin doesn't exist */
110 { 0, 0, 0, 0, 0, 0 }, /* PB02: pin doesn't exist */
111 { 0, 0, 0, 0, 0, 0 }, /* PB01: pin doesn't exist */
112 { 0, 0, 0, 0, 0, 0 } /* PB00: pin doesn't exist */
113 },
114
115 /* Port C configuration */
116 {
117 /* cnf par sor dir odr dat */
118 { 1, 0, 0, 0, 0, 0 }, /* PC31: MEZ ~IACK */
119 { 0, 0, 0, 0, 0, 0 }, /* PC30: ? */
120 { 1, 1, 0, 0, 0, 0 }, /* PC29: CLK SCCx */
121 { 1, 1, 0, 0, 0, 0 }, /* PC28: CLK4 */
122 { 1, 1, 0, 0, 0, 0 }, /* PC27: CLK SCCF */
123 { 1, 1, 0, 0, 0, 0 }, /* PC26: CLK 32K */
124 { 1, 1, 0, 0, 0, 0 }, /* PC25: BRG4/CLK7 */
125 { 0, 0, 0, 0, 0, 0 }, /* PC24: ? */
126 { 1, 1, 0, 0, 0, 0 }, /* PC23: CLK SCCx */
127 { 1, 1, 0, 0, 0, 0 }, /* PC22: FCC1 MII RX_CLK */
128 { 1, 1, 0, 0, 0, 0 }, /* PC21: FCC1 MII TX_CLK */
129 { 1, 1, 0, 0, 0, 0 }, /* PC20: CLK SCCF */
130 { 1, 1, 0, 0, 0, 0 }, /* PC19: FCC2 MII RX_CLK */
131 { 1, 1, 0, 0, 0, 0 }, /* PC18: FCC2 MII TX_CLK */
132 { 1, 1, 0, 0, 0, 0 }, /* PC17: FCC3 MII RX_CLK */
133 { 1, 1, 0, 0, 0, 0 }, /* PC16: FCC3 MII TX_CLK */
134 { 1, 0, 0, 0, 0, 0 }, /* PC15: SCC1 UART ~CTS */
135 { 1, 0, 0, 0, 0, 0 }, /* PC14: SCC1 UART ~CD */
136 { 1, 0, 0, 0, 0, 0 }, /* PC13: SCC2 UART ~CTS */
137 { 1, 0, 0, 0, 0, 0 }, /* PC12: SCC2 UART ~CD */
138 { 1, 0, 0, 1, 0, 0 }, /* PC11: SCC1 UART ~DTR */
139 { 1, 0, 0, 1, 0, 0 }, /* PC10: SCC1 UART ~DSR */
140 { 1, 0, 0, 1, 0, 0 }, /* PC09: SCC2 UART ~DTR */
141 { 1, 0, 0, 1, 0, 0 }, /* PC08: SCC2 UART ~DSR */
142 { 1, 0, 0, 0, 0, 0 }, /* PC07: TEMP ~ALERT */
143 { 1, 0, 0, 0, 0, 0 }, /* PC06: FCC3 INT */
144 { 1, 0, 0, 0, 0, 0 }, /* PC05: FCC2 INT */
145 { 1, 0, 0, 0, 0, 0 }, /* PC04: FCC1 INT */
146 { 0, 1, 1, 1, 0, 0 }, /* PC03: SDMA IDMA2 ~DACK */
147 { 0, 1, 1, 0, 0, 0 }, /* PC02: SDMA IDMA2 ~DONE */
148 { 0, 1, 0, 0, 0, 0 }, /* PC01: SDMA IDMA2 ~DREQ */
149 { 1, 1, 0, 1, 0, 0 } /* PC00: BRG7 */
150 },
151
152 /* Port D configuration */
153 {
154 /* cnf par sor dir odr dat */
155 { 1, 1, 0, 0, 0, 0 }, /* PD31: SCC1 UART RxD */
156 { 1, 1, 1, 1, 0, 0 }, /* PD30: SCC1 UART TxD */
157 { 1, 0, 0, 1, 0, 0 }, /* PD29: SCC1 UART ~RTS */
158 { 1, 1, 0, 0, 0, 0 }, /* PD28: SCC2 UART RxD */
159 { 1, 1, 0, 1, 0, 0 }, /* PD27: SCC2 UART TxD */
160 { 1, 0, 0, 1, 0, 0 }, /* PD26: SCC2 UART ~RTS */
161 { 1, 0, 0, 0, 0, 0 }, /* PD25: SCC1 UART ~RI */
162 { 1, 0, 0, 0, 0, 0 }, /* PD24: SCC2 UART ~RI */
163 { 1, 0, 0, 1, 0, 0 }, /* PD23: CLKGEN PD */
164 { 1, 0, 0, 0, 0, 0 }, /* PD22: USER3 */
165 { 1, 0, 0, 0, 0, 0 }, /* PD21: USER2 */
166 { 1, 0, 0, 0, 0, 0 }, /* PD20: USER1 */
167 { 1, 1, 1, 0, 0, 0 }, /* PD19: SPI ~SEL */
168 { 1, 1, 1, 0, 0, 0 }, /* PD18: SPI CLK */
169 { 1, 1, 1, 0, 0, 0 }, /* PD17: SPI MOSI */
170 { 1, 1, 1, 0, 0, 0 }, /* PD16: SPI MISO */
171 { 1, 1, 1, 0, 1, 0 }, /* PD15: I2C SDA */
172 { 1, 1, 1, 0, 1, 0 }, /* PD14: I2C SCL */
173 { 1, 0, 0, 1, 0, 1 }, /* PD13: TEMP ~STDBY */
174 { 1, 0, 0, 1, 0, 1 }, /* PD12: FCC3 ~RESET */
175 { 1, 0, 0, 1, 0, 1 }, /* PD11: FCC2 ~RESET */
176 { 1, 0, 0, 1, 0, 1 }, /* PD10: FCC1 ~RESET */
177 { 1, 0, 0, 0, 0, 0 }, /* PD09: PD9 */
178 { 1, 0, 0, 0, 0, 0 }, /* PD08: PD8 */
179 { 1, 0, 0, 1, 0, 1 }, /* PD07: PD7 */
180 { 1, 0, 0, 1, 0, 1 }, /* PD06: PD6 */
181 { 1, 0, 0, 1, 0, 1 }, /* PD05: PD5 */
182 { 1, 0, 0, 1, 0, 1 }, /* PD04: PD4 */
183 { 0, 0, 0, 0, 0, 0 }, /* PD03: pin doesn't exist */
184 { 0, 0, 0, 0, 0, 0 }, /* PD02: pin doesn't exist */
185 { 0, 0, 0, 0, 0, 0 }, /* PD01: pin doesn't exist */
186 { 0, 0, 0, 0, 0, 0 } /* PD00: pin doesn't exist */
187 }
16f21704
WD		 188};
189
190/* ------------------------------------------------------------------------- */
191
192/*
193 * AMI FS6377 Clock Generator configuration table
194 *
195 * the "fs6377_regs[]" table entries correspond to FS6377 registers
196 * 0 - 15 (total of 16 bytes).
197 *
198 * the data is written to the FS6377 via the i2c bus using address in
199 * "fs6377_addr" (address is 7 bits - R/W bit not included).
6dd652fa
WD		 200 *
201 * The fs6377 has four clock outputs: A, B, C and D.
202 *
203 * Outputs C and D can each provide two different clock outputs C1/D1 or
204 * C2/D2 depending on the state of the SEL_CD input which is connected to
205 * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
206 * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
207 *
208 * PA11 defaults to output low (or 0) in the i/o port config table above.
209 *
210 * Output A provides a 100MHz for the High Speed Serial chips. Output B
211 * provides a 3.6864MHz clock for more accurate asynchronous serial bit
212 * rates. Output C is routed to the mezzanine connector but is currently
213 * unused - both C1 and C2 are set to 16MHz. Output D is used by both the
214 * alt-input and display mezzanine boards for their video chips. The
215 * alt-input board requires a clock of 24.576MHz and this is available on
216 * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
217 * is available on D2 (PA11=SEL_CD=1).
218 *
219 * So the default is a clock suitable for the alt-input board. PA11 is toggled
220 * later in misc_init_r(), if a display board is detected.
16f21704
WD		 221 */
222
223uchar fs6377_addr = 0x5c;
224
225uchar fs6377_regs[16] = {
6dd652fa
WD		 226 12, 75, 64, 25, 144, 128, 25, 192,
227 0, 16, 135, 192, 224, 64, 64, 192
16f21704
WD		 228};
229
16f21704
WD		 230/* ------------------------------------------------------------------------- */
231
232/*
233 * special board initialisation, after clocks and timebase have been
234 * set up but before environment and serial are initialised.
235 *
236 * added so that very early initialisations can be done using the i2c
237 * driver (which requires the clocks, to calculate the dividers, and
238 * the timebase, for udelay())
239 */
240
6dd652fa
WD		 241int
242board_postclk_init (void)
16f21704 243{
6d0f6bcf 244 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
16f21704
WD		 245
246 /*
247 * Initialise the FS6377 clock chip
248 *
249 * the secondary address is the register number from where to
250 * start the write - I want to write all the registers
251 *
252 * don't bother checking return status - we have no console yet
253 * to print it on, nor any RAM to store it in - it will be obvious
254 * if this doesn't work
255 */
256 (void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
6dd652fa 257 sizeof (fs6377_regs));
16f21704
WD		 258
259 return (0);
260}
261
262/* ------------------------------------------------------------------------- */
263
264/*
265 * Check Board Identity: Hardwired to HYMOD
266 */
267
6dd652fa
WD		 268int
269checkboard (void)
16f21704
WD		 270{
271 puts ("Board: HYMOD\n");
272 return (0);
273}
274
275/* ------------------------------------------------------------------------- */
276
277/*
278 * miscellaneous (early - while running in flash) initialisations.
279 */
280
281#define _NOT_USED_ 0xFFFFFFFF
282
283uint upmb_table[] = {
284 /* Read Single Beat (RSS) - offset 0x00 */
285 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
286 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
287 /* Read Burst (RBS) - offset 0x08 */
288 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
289 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
290 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
291 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
292 /* Write Single Beat (WSS) - offset 0x18 */
293 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
294 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
295 /* Write Burst (WSS) - offset 0x20 */
296 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
297 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
298 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
299 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
300 /* Refresh Timer (PTS) - offset 0x30 */
301 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
302 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
303 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
304 /* Exception Condition (EXS) - offset 0x3c */
305 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
306};
307
308uint upmc_table[] = {
309 /* Read Single Beat (RSS) - offset 0x00 */
310 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
311 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
312 /* Read Burst (RBS) - offset 0x08 */
313 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
314 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
315 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
316 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
317 /* Write Single Beat (WSS) - offset 0x18 */
318 0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
319 0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
320 /* Write Burst (WSS) - offset 0x20 */
321 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
322 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
323 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
324 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
325 /* Refresh Timer (PTS) - offset 0x30 */
326 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
327 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
328 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
329 /* Exception Condition (EXS) - offset 0x3c */
330 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
331};
332
6dd652fa
WD		 333int
334misc_init_f (void)
16f21704 335{
6d0f6bcf 336 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
16f21704
WD		 337 volatile memctl8260_t *memctl = &immap->im_memctl;
338
339 printf ("UPMs: ");
340
341 upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
6d0f6bcf 342 memctl->memc_mbmr = CONFIG_SYS_MBMR;
16f21704
WD		 343
344 upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
6d0f6bcf 345 memctl->memc_mcmr = CONFIG_SYS_MCMR;
16f21704
WD		 346
347 printf ("configured\n");
348 return (0);
349}
350
351/* ------------------------------------------------------------------------- */
352
9973e3c6 353phys_size_t
6dd652fa 354initdram (int board_type)
16f21704 355{
6d0f6bcf 356 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
16f21704 357 volatile memctl8260_t *memctl = &immap->im_memctl;
6d0f6bcf
JCPV		 358 volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
359 ulong psdmr = CONFIG_SYS_PSDMR;
16f21704
WD		 360 int i;
361
362 /*
363 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
364 *
365 * "At system reset, initialization software must set up the
366 * programmable parameters in the memory controller banks registers
fa82f871 367 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
16f21704
WD		 368 * system software should execute the following initialization sequence
369 * for each SDRAM device.
370 *
371 * 1. Issue a PRECHARGE-ALL-BANKS command
372 * 2. Issue eight CBR REFRESH commands
373 * 3. Issue a MODE-SET command to initialize the mode register
374 *
375 * The initial commands are executed by setting P/LSDMR[OP] and
376 * accessing the SDRAM with a single-byte transaction."
377 *
378 * The appropriate BRx/ORx registers have already been set when we
6d0f6bcf 379 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
16f21704
WD		 380 */
381
6d0f6bcf
JCPV		 382 memctl->memc_psrt = CONFIG_SYS_PSRT;
383 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
16f21704
WD		 384
385 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
386 *ramaddr = c;
387
388 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
389 for (i = 0; i < 8; i++)
390 *ramaddr = c;
391
392 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
393 *ramaddr = c;
394
395 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
396 *ramaddr = c;
397
6d0f6bcf 398 return (CONFIG_SYS_SDRAM_SIZE << 20);
16f21704
WD		 399}
400
401/* ------------------------------------------------------------------------- */
402/* miscellaneous initialisations after relocation into ram (misc_init_r) */
53677ef1 403/* */
16f21704
WD		 404/* loads the data in the main board and mezzanine board eeproms into */
405/* the hymod configuration struct stored in the board information area. */
53677ef1 406/* */
16f21704
WD		 407/* if the contents of either eeprom is invalid, prompts for a serial */
408/* number (and an ethernet address if required) then fetches a file */
409/* containing information to be stored in the eeprom from the tftp server */
410/* (the file name is based on the serial number and a built-in path) */
411
6dd652fa
WD		 412int
413last_stage_init (void)
16f21704 414{
16f21704
WD		 415 hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
416 int rc;
417
6dd652fa
WD		 418#ifdef CONFIG_BOOT_RETRY_TIME
419 /*
e1bf824d 420 * we use the cli_readline() function, but we also want
6dd652fa
WD		 421 * command timeout enabled
422 */
423 init_cmd_timeout ();
424#endif
425
16f21704
WD		 426 memset ((void *) cp, 0, sizeof (*cp));
427
428 /* set up main board config info */
429
6dd652fa
WD		 430 rc = hymod_eeprom_read (0, &cp->main.eeprom);
431
432 puts ("EEPROM:main...");
433 if (rc < 0)
434 puts ("NOT PRESENT\n");
435 else if (rc == 0)
436 puts ("INVALID\n");
437 else {
438 cp->main.eeprom.valid = 1;
439
440 printf ("OK (ver %u)\n", cp->main.eeprom.ver);
441 hymod_eeprom_print (&cp->main.eeprom);
442
443 /*
444 * hard-wired assumption here: all hymod main boards will have
445 * one xilinx fpga, with the interrupt line connected to IRQ2
446 *
447 * One day, this might be based on the board type
448 */
449
450 cp->main.xlx[0].mmap.prog.exists = 1;
451 cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
452 cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
453
454 cp->main.xlx[0].mmap.reg.exists = 1;
455 cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
456 cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
457
458 cp->main.xlx[0].mmap.port.exists = 1;
459 cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
460 cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
461
462 cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
463 cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
464 cp->main.xlx[0].iopins.prog_pin.flag = 1;
465 cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
466 cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
467 cp->main.xlx[0].iopins.init_pin.flag = 1;
468 cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
469 cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
470 cp->main.xlx[0].iopins.done_pin.flag = 1;
16f21704 471#ifdef FPGA_MAIN_ENABLE_PORT
6dd652fa
WD		 472 cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
473 cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
474 cp->main.xlx[0].iopins.enable_pin.flag = 1;
16f21704 475#endif
16f21704 476
6dd652fa
WD		 477 cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
478 }
16f21704 479
6dd652fa 480 /* set up mezzanine board config info */
16f21704 481
6dd652fa 482 rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
16f21704 483
6dd652fa
WD		 484 puts ("EEPROM:mezz...");
485 if (rc < 0)
486 puts ("NOT PRESENT\n");
487 else if (rc == 0)
488 puts ("INVALID\n");
489 else {
490 cp->main.eeprom.valid = 1;
16f21704 491
6dd652fa
WD		 492 printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
493 hymod_eeprom_print (&cp->mezz.eeprom);
494 }
16f21704 495
6dd652fa 496 cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
16f21704 497
6dd652fa 498 hymod_check_env ();
16f21704 499
16f21704
WD		 500 return (0);
501}
a8c7c708
WD		 502
503#ifdef CONFIG_SHOW_ACTIVITY
504void board_show_activity (ulong timebase)
505{
6d0f6bcf
JCPV		 506#ifdef CONFIG_SYS_HYMOD_DBLEDS
507 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
a8c7c708
WD		 508 volatile iop8260_t *iop = &immr->im_ioport;
509 static int shift = 0;
510
6d0f6bcf 511 if ((timestamp % CONFIG_SYS_HZ) == 0) {
a8c7c708
WD		 512 if (++shift > 3)
513 shift = 0;
514 iop->iop_pdatd =
515 (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
516 }
6d0f6bcf 517#endif /* CONFIG_SYS_HYMOD_DBLEDS */
a8c7c708
WD		 518}
519
520void show_activity(int arg)
521{
522}
523#endif /* CONFIG_SHOW_ACTIVITY */
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