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945af8d7 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <mpc5xxx.h> | |
96e48cf6 | 26 | #include <pci.h> |
945af8d7 | 27 | |
e0ac62d7 | 28 | static long int dram_size(long int *base, long int maxsize) |
945af8d7 | 29 | { |
e0ac62d7 WD |
30 | volatile long int *addr; |
31 | ulong cnt, val; | |
32 | ulong save[32]; /* to make test non-destructive */ | |
33 | unsigned char i = 0; | |
945af8d7 | 34 | |
e0ac62d7 WD |
35 | for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { |
36 | addr = base + cnt; /* pointer arith! */ | |
37 | ||
38 | save[i++] = *addr; | |
39 | *addr = ~cnt; | |
40 | } | |
41 | ||
42 | /* write 0 to base address */ | |
43 | addr = base; | |
44 | save[i] = *addr; | |
45 | *addr = 0; | |
46 | ||
47 | /* check at base address */ | |
48 | if ((val = *addr) != 0) { | |
49 | *addr = save[i]; | |
50 | return (0); | |
51 | } | |
52 | ||
53 | for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { | |
54 | addr = base + cnt; /* pointer arith! */ | |
55 | ||
56 | val = *addr; | |
57 | *addr = save[--i]; | |
58 | ||
59 | if (val != (~cnt)) { | |
60 | return (cnt * sizeof (long)); | |
61 | } | |
62 | } | |
63 | return (maxsize); | |
64 | } | |
65 | ||
66 | static void sdram_start (int hi_addr) | |
67 | { | |
68 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
945af8d7 WD |
69 | |
70 | /* unlock mode register */ | |
e0ac62d7 | 71 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit; |
945af8d7 | 72 | /* precharge all banks */ |
e0ac62d7 | 73 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit; |
945af8d7 | 74 | /* set mode register */ |
e0ac62d7 | 75 | #if defined(CONFIG_MPC5200) |
945af8d7 | 76 | *(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000; |
e0ac62d7 WD |
77 | #elif defined(CONFIG_MGT5100) |
78 | *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; | |
79 | #endif | |
945af8d7 | 80 | /* precharge all banks */ |
e0ac62d7 | 81 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit; |
945af8d7 | 82 | /* auto refresh */ |
e0ac62d7 | 83 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit; |
945af8d7 WD |
84 | /* set mode register */ |
85 | *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; | |
86 | /* normal operation */ | |
e0ac62d7 WD |
87 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit; |
88 | } | |
89 | ||
90 | long int initdram (int board_type) | |
91 | { | |
92 | ulong test1, test2, dramsize = 0; | |
93 | #ifndef CFG_RAMBOOT | |
94 | /* configure SDRAM start/end */ | |
95 | #if defined(CONFIG_MPC5200) | |
96 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ | |
97 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ | |
98 | ||
99 | /* setup config registers */ | |
100 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00; | |
101 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004; | |
102 | ||
945af8d7 WD |
103 | #elif defined(CONFIG_MGT5100) |
104 | *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; | |
e0ac62d7 | 105 | *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ |
945af8d7 WD |
106 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ |
107 | ||
108 | /* setup config registers */ | |
109 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600; | |
110 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004; | |
111 | ||
112 | /* address select register */ | |
113 | *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000; | |
945af8d7 | 114 | #endif |
e0ac62d7 WD |
115 | sdram_start(0); |
116 | test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); | |
117 | sdram_start(1); | |
118 | test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); | |
119 | if (test1 > test2) { | |
120 | sdram_start(0); | |
121 | dramsize = test1; | |
122 | } else { | |
123 | dramsize = test2; | |
124 | } | |
125 | #if defined(CONFIG_MPC5200) | |
126 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = | |
127 | (0x13 + __builtin_ffs(dramsize >> 20) - 1); | |
128 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ | |
129 | #elif defined(CONFIG_MGT5100) | |
130 | *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); | |
131 | #endif | |
132 | ||
945af8d7 WD |
133 | #else |
134 | #ifdef CONFIG_MGT5100 | |
135 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ | |
136 | #endif | |
137 | #endif | |
138 | /* return total ram size */ | |
e0ac62d7 | 139 | return dramsize; |
945af8d7 WD |
140 | } |
141 | ||
142 | int checkboard (void) | |
143 | { | |
144 | #if defined(CONFIG_MPC5200) | |
145 | puts ("Board: Motorola MPC5200 (IceCube)\n"); | |
146 | #elif defined(CONFIG_MGT5100) | |
147 | puts ("Board: Motorola MGT5100 (IceCube)\n"); | |
148 | #endif | |
149 | return 0; | |
150 | } | |
151 | ||
152 | void flash_preinit(void) | |
153 | { | |
154 | /* | |
155 | * Now, when we are in RAM, enable flash write | |
156 | * access for detection process. | |
157 | * Note that CS_BOOT cannot be cleared when | |
158 | * executing in flash. | |
159 | */ | |
160 | #if defined(CONFIG_MGT5100) | |
161 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ | |
162 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ | |
163 | #endif | |
164 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ | |
165 | } | |
96e48cf6 WD |
166 | |
167 | #ifdef CONFIG_PCI | |
168 | static struct pci_controller hose; | |
169 | ||
170 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
171 | ||
172 | void pci_init_board(void) | |
173 | { | |
174 | pci_mpc5xxx_init(&hose); | |
175 | } | |
176 | #endif |