[thirdparty/u-boot.git] / board / ids8247 / ids8247.c

/*
 * (C) Copyright 2005
 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ioports.h>
#include <mpc8260.h>

#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {	/*	      conf ppar psor pdir podr pdat */
	/* PA31 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
	/* PA30 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
	/* PA29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
	/* PA28 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
	/* PA27 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
	/* PA26 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
	/* PA25 */ {   0,   0,	 0,   0,   1,	0   }, /* 8247_P0 */
#if defined(CONFIG_SYS_I2C_SOFT)
	/* PA24 */ {   1,   0,	 0,   0,   1,	1   }, /* I2C_SDA2 */
	/* PA23 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C_SCL2 */
#else /* normal I/O port pins */
	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* PA24 */
	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* PA23 */
#endif
	/* PA22 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DCD */
	/* PA21 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
	/* PA20 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
	/* PA19 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
	/* PA18 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
	/* PA17 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
	/* PA16 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
	/* PA15 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
	/* PA14 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
	/* PA13 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_RTS */
	/* PA12 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_CTS */
	/* PA11 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_DTR */
	/* PA10 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DSR */
	/* PA9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
	/* PA8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
    },

    /* Port B configuration */
    {	/*	      conf ppar psor pdir podr pdat */
	/* PB31 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
	/* PB26 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
	/* PB25 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
    },

    /* Port C */
    {	/*	      conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
	/* PC29 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_OUT */
	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
	/* PC25 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_IN */
	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
	/* PC23 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 MII TX_CLK */
	/* PC22 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 MII RX_CLK */
	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
	/* PC16 */ {   0,   0,	 0,   1,   0,	0   }, /* PC16 */
	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDC */
	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDIO */
	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
    },

    /* Port D */
    {	/*	      conf ppar psor pdir podr pdat */
	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
	/* PD25 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC3_RX */
	/* PD24 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_TX */
	/* PD23 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_RTS */
	/* PD22 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC4_RXD */
	/* PD21 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_TXD */
	/* PD20 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_RTS */
	/* PD19 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_SEL */
	/* PD18 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_CLK */
	/* PD17 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MOSI */
	/* PD16 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MISO */
#if defined(CONFIG_HARD_I2C)
	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA1 */
	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL1 */
#else /* normal I/O port pins */
	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* PD15 */
	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* PD14 */
#endif
	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
	/* PD9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD9 */
	/* PD8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD8 */
	/* PD7	*/ {   1,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
    }
};

/* ------------------------------------------------------------------------- */

/* Check Board Identity:
 */
int checkboard (void)
{
	puts ("Board: IDS 8247\n");
	return 0;
}

/* ------------------------------------------------------------------------- */

/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 *
 * This routine performs standard 8260 initialization sequence
 * and calculates the available memory size. It may be called
 * several times to try different SDRAM configurations on both
 * 60x and local buses.
 */
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
						  ulong orx, volatile uchar * base)
{
	volatile uchar c = 0xff;
	volatile uint *sdmr_ptr;
	volatile uint *orx_ptr;
	ulong maxsize, size;
	int i;

	/* We must be able to test a location outsize the maximum legal size
	 * to find out THAT we are outside; but this address still has to be
	 * mapped by the controller. That means, that the initial mapping has
	 * to be (at least) twice as large as the maximum expected size.
	 */
	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;

	sdmr_ptr = &memctl->memc_psdmr;
	orx_ptr = &memctl->memc_or2;

	*orx_ptr = orx;

	/*
	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	 *
	 * "At system reset, initialization software must set up the
	 *  programmable parameters in the memory controller banks registers
	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	 *  system software should execute the following initialization sequence
	 *  for each SDRAM device.
	 *
	 *  1. Issue a PRECHARGE-ALL-BANKS command
	 *  2. Issue eight CBR REFRESH commands
	 *  3. Issue a MODE-SET command to initialize the mode register
	 *
	 *  The initial commands are executed by setting P/LSDMR[OP] and
	 *  accessing the SDRAM with a single-byte transaction."
	 *
	 * The appropriate BRx/ORx registers have already been set when we
	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
	 */

	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
	*base = c;

	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
	for (i = 0; i < 8; i++)
		*base = c;

	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */

	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
	*base = c;

	size = get_ram_size((long *)base, maxsize);
	*orx_ptr = orx | ~(size - 1);

	return (size);
}

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;

	long psize;

	psize = 16 * 1024 * 1024;

	memctl->memc_psrt = CONFIG_SYS_PSRT;
	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

#ifndef CONFIG_SYS_RAMBOOT
	/* 60x SDRAM setup:
	 */
	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
						  (uchar *) CONFIG_SYS_SDRAM_BASE);
#endif /* CONFIG_SYS_RAMBOOT */

	icache_enable ();

	return (psize);
}

int misc_init_r (void)
{
	gd->bd->bi_flashstart = 0xff800000;
	return 0;
}

#if defined(CONFIG_CMD_NAND)
#include <nand.h>
#include <linux/mtd/mtd.h>
#include <asm/io.h>

static u8 hwctl;

static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *this = mtd->priv;

	if (ctrl & NAND_CTRL_CHANGE) {
		if ( ctrl & NAND_CLE ) {
			hwctl |= 0x1;
			writeb(0x00, (this->IO_ADDR_W + 0x0a));
		} else {
			hwctl &= ~0x1;
			writeb(0x00, (this->IO_ADDR_W + 0x08));
		}
		if ( ctrl & NAND_ALE ) {
			hwctl |= 0x2;
			writeb(0x00, (this->IO_ADDR_W + 0x09));
		} else {
			hwctl &= ~0x2;
			writeb(0x00, (this->IO_ADDR_W + 0x08));
		}
		if ( (ctrl & NAND_NCE) != NAND_NCE)
			writeb(0x00, (this->IO_ADDR_W + 0x0c));
		else
			writeb(0x00, (this->IO_ADDR_W + 0x08));
	}
	if (cmd != NAND_CMD_NONE)
		writeb(cmd, this->IO_ADDR_W);

}

static u_char ids_nand_read_byte(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd->priv;

	return readb(this->IO_ADDR_R);
}

static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
	struct nand_chip *nand = mtd->priv;
	int i;

	for (i = 0; i < len; i++) {
		if (hwctl & 0x1)
			writeb(buf[i], (nand->IO_ADDR_W + 0x02));
		else if (hwctl & 0x2)
			writeb(buf[i], (nand->IO_ADDR_W + 0x01));
		else
			writeb(buf[i], nand->IO_ADDR_W);
	}
}

static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
	struct nand_chip *this = mtd->priv;
	int i;

	for (i = 0; i < len; i++) {
		buf[i] = readb(this->IO_ADDR_R);
	}
}

static int ids_nand_dev_ready(struct mtd_info *mtd)
{
	/* constant delay (see also tR in the datasheet) */
	udelay(12);
	return 1;
}

int board_nand_init(struct nand_chip *nand)
{
	nand->ecc.mode = NAND_ECC_SOFT;

	/* Reference hardware control function */
	nand->cmd_ctrl  = ids_nand_hwctrl;
	nand->read_byte  = ids_nand_read_byte;
	nand->write_buf  = ids_nand_write_buf;
	nand->read_buf   = ids_nand_read_buf;
	nand->dev_ready  = ids_nand_dev_ready;
	nand->chip_delay = 12;

	return 0;
}

#endif	/* CONFIG_CMD_NAND */

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup( blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
Commit	Line	Data
9dd41a7b WD	1	/*
	2	* (C) Copyright 2005
	3	* Heiko Schocher, DENX Software Engineering, <hs@denx.de>
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
9dd41a7b WD	6	*/
	7
	8	#include <common.h>
	9	#include <ioports.h>
	10	#include <mpc8260.h>
	11
6abd82e1 SS	12	#if defined(CONFIG_OF_LIBFDT)
	13	#include <libfdt.h>
	14	#include <libfdt_env.h>
	15	#include <fdt_support.h>
	16	#endif
	17
d87080b7 WD	18	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	19
9dd41a7b WD	20	/*
	21	* I/O Port configuration table
	22	*
	23	* if conf is 1, then that port pin will be configured at boot time
	24	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	25	*/
	26
	27	const iop_conf_t iop_conf_tab[4][32] = {
	28
	29	/* Port A configuration */
	30	{ /* conf ppar psor pdir podr pdat */
6abd82e1 SS	31	/* PA31 / { 1, 1, 1, 0, 0, 0 }, / FCC1 COL */
	32	/* PA30 / { 1, 1, 1, 0, 0, 0 }, / FCC1 CRS */
	33	/* PA29 / { 1, 1, 1, 1, 0, 0 }, / FCC1 TXER */
	34	/* PA28 / { 1, 1, 1, 1, 0, 0 }, / FCC1 TXEN */
	35	/* PA27 / { 1, 1, 1, 0, 0, 0 }, / FCC1 RXDV */
	36	/* PA26 / { 1, 1, 1, 0, 0, 0 }, / FCC1 RXER */
9dd41a7b	37	/* PA25 / { 0, 0, 0, 0, 1, 0 }, / 8247_P0 */
ea818dbb	38	#if defined(CONFIG_SYS_I2C_SOFT)
9dd41a7b WD	39	/* PA24 / { 1, 0, 0, 0, 1, 1 }, / I2C_SDA2 */
	40	/* PA23 / { 1, 0, 0, 1, 1, 1 }, / I2C_SCL2 */
	41	#else /* normal I/O port pins */
	42	/* PA24 / { 0, 0, 0, 1, 0, 0 }, / PA24 */
	43	/* PA23 / { 0, 0, 0, 1, 0, 0 }, / PA23 */
	44	#endif
	45	/* PA22 / { 0, 0, 0, 0, 1, 0 }, / SMC2_DCD */
6abd82e1 SS	46	/* PA21 / { 1, 1, 0, 1, 0, 0 }, / FCC1 TXD3 */
	47	/* PA20 / { 1, 1, 0, 1, 0, 0 }, / FCC1 TXD2 */
	48	/* PA19 / { 1, 1, 0, 1, 0, 0 }, / FCC1 TXD1 */
	49	/* PA18 / { 1, 1, 0, 1, 0, 0 }, / FCC1 TXD0 */
	50	/* PA17 / { 1, 1, 0, 0, 0, 0 }, / FCC1 RXD0 */
	51	/* PA16 / { 1, 1, 0, 0, 0, 0 }, / FCC1 RXD1 */
	52	/* PA15 / { 1, 1, 0, 0, 0, 0 }, / FCC1 RXD2 */
	53	/* PA14 / { 1, 1, 0, 0, 0, 0 }, / FCC1 RXD3 */
9dd41a7b WD	54	/* PA13 / { 0, 0, 0, 1, 1, 0 }, / SMC2_RTS */
	55	/* PA12 / { 0, 0, 0, 0, 1, 0 }, / SMC2_CTS */
	56	/* PA11 / { 0, 0, 0, 1, 1, 0 }, / SMC2_DTR */
	57	/* PA10 / { 0, 0, 0, 0, 1, 0 }, / SMC2_DSR */
	58	/* PA9 / { 0, 1, 0, 1, 0, 0 }, / SMC2 TXD */
	59	/* PA8 / { 0, 1, 0, 0, 0, 0 }, / SMC2 RXD */
	60	/* PA7 / { 0, 0, 0, 1, 0, 0 }, / PA7 */
	61	/* PA6 / { 0, 0, 0, 1, 0, 0 }, / PA6 */
	62	/* PA5 / { 0, 0, 0, 1, 0, 0 }, / PA5 */
	63	/* PA4 / { 0, 0, 0, 1, 0, 0 }, / PA4 */
	64	/* PA3 / { 0, 0, 0, 1, 0, 0 }, / PA3 */
	65	/* PA2 / { 0, 0, 0, 1, 0, 0 }, / PA2 */
	66	/* PA1 / { 0, 0, 0, 1, 0, 0 }, / PA1 */
	67	/* PA0 / { 0, 0, 0, 1, 0, 0 } / PA0 */
	68	},
	69
	70	/* Port B configuration */
	71	{ /* conf ppar psor pdir podr pdat */
6abd82e1 SS	72	/* PB31 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	73	/* PB30 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	74	/* PB29 / { 0, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	75	/* PB28 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	76	/* PB27 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	77	/* PB26 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	78	/* PB25 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	79	/* PB24 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	80	/* PB23 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	81	/* PB22 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	82	/* PB21 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	83	/* PB20 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	84	/* PB19 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
	85	/* PB18 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
9dd41a7b WD	86	/* PB17 / { 0, 0, 0, 0, 0, 0 }, / PB17 */
	87	/* PB16 / { 0, 0, 0, 0, 0, 0 }, / PB16 */
	88	/* PB15 / { 0, 0, 0, 0, 0, 0 }, / PB15 */
	89	/* PB14 / { 0, 0, 0, 0, 0, 0 }, / PB14 */
	90	/* PB13 / { 0, 0, 0, 0, 0, 0 }, / PB13 */
	91	/* PB12 / { 0, 0, 0, 0, 0, 0 }, / PB12 */
	92	/* PB11 / { 0, 0, 0, 0, 0, 0 }, / PB11 */
	93	/* PB10 / { 0, 0, 0, 0, 0, 0 }, / PB10 */
	94	/* PB9 / { 0, 0, 0, 0, 0, 0 }, / PB9 */
	95	/* PB8 / { 0, 0, 0, 0, 0, 0 }, / PB8 */
	96	/* PB7 / { 0, 0, 0, 0, 0, 0 }, / PB7 */
	97	/* PB6 / { 0, 0, 0, 0, 0, 0 }, / PB6 */
	98	/* PB5 / { 0, 0, 0, 0, 0, 0 }, / PB5 */
	99	/* PB4 / { 0, 0, 0, 0, 0, 0 }, / PB4 */
	100	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	101	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	102	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	103	/* PB0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
	104	},
	105
	106	/* Port C */
	107	{ /* conf ppar psor pdir podr pdat */
	108	/* PC31 / { 0, 0, 0, 1, 0, 0 }, / PC31 */
	109	/* PC30 / { 0, 0, 0, 1, 0, 0 }, / PC30 */
	110	/* PC29 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CLSN /
	111	/* PC28 / { 0, 1, 1, 0, 0, 0 }, / SYNC_OUT */
	112	/* PC27 / { 0, 0, 0, 1, 0, 0 }, / PC27 */
	113	/* PC26 / { 0, 0, 0, 1, 0, 0 }, / PC26 */
	114	/* PC25 / { 0, 1, 1, 0, 0, 0 }, / SYNC_IN */
	115	/* PC24 / { 0, 0, 0, 1, 0, 0 }, / PC24 */
6abd82e1 SS	116	/* PC23 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII TX_CLK */
6abd82e1 SS	117	/* PC22 / { 1, 1, 0, 0, 0, 0 }, / FCC1 MII RX_CLK */
9dd41a7b WD	118	/* PC21 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN RXCLK */
	119	/* PC20 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN TXCLK */
	120	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK */
	121	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII TX_CLK */
	122	/* PC17 / { 0, 0, 0, 1, 0, 0 }, / PC17 */
	123	/* PC16 / { 0, 0, 0, 1, 0, 0 }, / PC16 */
	124	/* PC15 / { 0, 0, 0, 1, 0, 0 }, / PC15 */
	125	/* PC14 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CD /
	126	/* PC13 / { 0, 0, 0, 1, 0, 0 }, / PC13 */
	127	/* PC12 / { 0, 0, 0, 1, 0, 0 }, / PC12 */
	128	/* PC11 / { 0, 0, 0, 1, 0, 0 }, / PC11 */
	129	/* PC10 / { 0, 0, 0, 1, 0, 0 }, / FCC2 MDC */
	130	/* PC9 / { 0, 0, 0, 1, 0, 0 }, / FCC2 MDIO */
	131	/* PC8 / { 0, 0, 0, 1, 0, 0 }, / PC8 */
	132	/* PC7 / { 0, 0, 0, 1, 0, 0 }, / PC7 */
	133	/* PC6 / { 0, 0, 0, 1, 0, 0 }, / PC6 */
	134	/* PC5 / { 0, 0, 0, 1, 0, 0 }, / PC5 */
	135	/* PC4 / { 0, 0, 0, 1, 0, 0 }, / PC4 */
	136	/* PC3 / { 0, 0, 0, 1, 0, 0 }, / PC3 */
	137	/* PC2 / { 0, 0, 0, 1, 0, 1 }, / ENET FDE */
	138	/* PC1 / { 0, 0, 0, 1, 0, 0 }, / ENET DSQE */
	139	/* PC0 / { 0, 0, 0, 1, 0, 0 }, / ENET LBK */
	140	},
	141
	142	/* Port D */
	143	{ /* conf ppar psor pdir podr pdat */
	144	/* PD31 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN RxD */
	145	/* PD30 / { 0, 1, 1, 1, 0, 0 }, / SCC1 EN TxD */
	146	/* PD29 / { 0, 1, 0, 1, 0, 0 }, / SCC1 EN TENA */
	147	/* PD28 / { 0, 0, 0, 1, 0, 0 }, / PD28 */
	148	/* PD27 / { 0, 0, 0, 1, 0, 0 }, / PD27 */
	149	/* PD26 / { 0, 0, 0, 1, 0, 0 }, / PD26 */
	150	/* PD25 / { 0, 1, 0, 0, 0, 0 }, / SCC3_RX */
	151	/* PD24 / { 0, 1, 0, 1, 0, 0 }, / SCC3_TX */
	152	/* PD23 / { 0, 1, 0, 1, 0, 0 }, / SCC3_RTS */
	153	/* PD22 / { 0, 1, 0, 0, 0, 0 }, / SCC4_RXD */
	154	/* PD21 / { 0, 1, 0, 1, 0, 0 }, / SCC4_TXD */
	155	/* PD20 / { 0, 1, 0, 1, 0, 0 }, / SCC4_RTS */
	156	/* PD19 / { 0, 1, 1, 0, 0, 0 }, / SPI_SEL */
	157	/* PD18 / { 0, 1, 1, 0, 0, 0 }, / SPI_CLK */
	158	/* PD17 / { 0, 1, 1, 0, 0, 0 }, / SPI_MOSI */
	159	/* PD16 / { 0, 1, 1, 0, 0, 0 }, / SPI_MISO */
	160	#if defined(CONFIG_HARD_I2C)
	161	/* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA1 */
	162	/* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL1 */
	163	#else /* normal I/O port pins */
	164	/* PD15 / { 0, 1, 1, 0, 1, 0 }, / PD15 */
	165	/* PD14 / { 0, 1, 1, 0, 1, 0 }, / PD14 */
	166	#endif
	167	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
	168	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
	169	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
	170	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
	171	/* PD9 / { 0, 0, 0, 0, 0, 0 }, / PD9 */
	172	/* PD8 / { 0, 0, 0, 0, 0, 0 }, / PD8 */
6abd82e1	173	/* PD7 / { 1, 0, 0, 1, 0, 1 }, / MII_MDIO */
9dd41a7b WD	174	/* PD6 / { 0, 0, 0, 1, 0, 1 }, / PD6 */
	175	/* PD5 / { 0, 0, 0, 1, 0, 1 }, / PD5 */
	176	/* PD4 / { 0, 0, 0, 1, 0, 1 }, / PD4 */
	177	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	178	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	179	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	180	/* PD0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
	181	}
	182	};
	183
	184	/* ------------------------------------------------------------------------- */
	185
	186	/* Check Board Identity:
	187	*/
	188	int checkboard (void)
	189	{
	190	puts ("Board: IDS 8247\n");
	191	return 0;
	192	}
	193
	194	/* ------------------------------------------------------------------------- */
	195
	196	/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
	197	*
	198	* This routine performs standard 8260 initialization sequence
	199	* and calculates the available memory size. It may be called
	200	* several times to try different SDRAM configurations on both
	201	* 60x and local buses.
	202	*/
	203	static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
	204	ulong orx, volatile uchar * base)
	205	{
	206	volatile uchar c = 0xff;
	207	volatile uint *sdmr_ptr;
	208	volatile uint *orx_ptr;
	209	ulong maxsize, size;
	210	int i;
	211
	212	/* We must be able to test a location outsize the maximum legal size
	213	* to find out THAT we are outside; but this address still has to be
	214	* mapped by the controller. That means, that the initial mapping has
	215	* to be (at least) twice as large as the maximum expected size.
	216	*/
6abd82e1	217	maxsize = (1 + (~orx \| 0x7fff))/* / 2*/;
9dd41a7b WD	218
	219	sdmr_ptr = &memctl->memc_psdmr;
	220	orx_ptr = &memctl->memc_or2;
	221
	222	*orx_ptr = orx;
	223
	224	/*
	225	* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	226	*
	227	* "At system reset, initialization software must set up the
	228	* programmable parameters in the memory controller banks registers
	229	* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
	230	* system software should execute the following initialization sequence
	231	* for each SDRAM device.
	232	*
	233	* 1. Issue a PRECHARGE-ALL-BANKS command
	234	* 2. Issue eight CBR REFRESH commands
	235	* 3. Issue a MODE-SET command to initialize the mode register
	236	*
	237	* The initial commands are executed by setting P/LSDMR[OP] and
	238	* accessing the SDRAM with a single-byte transaction."
	239	*
	240	* The appropriate BRx/ORx registers have already been set when we
6d0f6bcf	241	* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
9dd41a7b WD	242	*/
	243
	244	*sdmr_ptr = sdmr \| PSDMR_OP_PREA;
	245	*base = c;
	246
	247	*sdmr_ptr = sdmr \| PSDMR_OP_CBRR;
	248	for (i = 0; i < 8; i++)
	249	*base = c;
	250
	251	*sdmr_ptr = sdmr \| PSDMR_OP_MRW;
6d0f6bcf	252	(base + CONFIG_SYS_MRS_OFFS) = c; / setting MR on address lines */
9dd41a7b WD	253
	254	*sdmr_ptr = sdmr \| PSDMR_OP_NORM \| PSDMR_RFEN;
	255	*base = c;
	256
	257	size = get_ram_size((long *)base, maxsize);
	258	*orx_ptr = orx \| ~(size - 1);
	259
	260	return (size);
	261	}
	262
9973e3c6	263	phys_size_t initdram (int board_type)
9dd41a7b	264	{
6d0f6bcf	265	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
9dd41a7b WD	266	volatile memctl8260_t *memctl = &immap->im_memctl;
9dd41a7b WD	267
d7251240	268	long psize;
9dd41a7b WD	269
9dd41a7b WD	270	psize = 16 * 1024 * 1024;
9dd41a7b	271
6d0f6bcf JCPV	272	memctl->memc_psrt = CONFIG_SYS_PSRT;
6d0f6bcf JCPV	273	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
9dd41a7b	274
6d0f6bcf	275	#ifndef CONFIG_SYS_RAMBOOT
9dd41a7b WD	276	/* 60x SDRAM setup:
9dd41a7b WD	277	*/
6d0f6bcf JCPV	278	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
	279	(uchar *) CONFIG_SYS_SDRAM_BASE);
	280	#endif /* CONFIG_SYS_RAMBOOT */
9dd41a7b WD	281
	282	icache_enable ();
	283
	284	return (psize);
	285	}
	286
	287	int misc_init_r (void)
	288	{
9dd41a7b	289	gd->bd->bi_flashstart = 0xff800000;
28afe016	290	return 0;
9dd41a7b WD	291	}
9dd41a7b WD	292
c508a4ce	293	#if defined(CONFIG_CMD_NAND)
28afe016 HS	294	#include <nand.h>
	295	#include <linux/mtd/mtd.h>
	296	#include <asm/io.h>
	297
	298	static u8 hwctl;
	299
	300	static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	301	{
	302	struct nand_chip *this = mtd->priv;
	303
	304	if (ctrl & NAND_CTRL_CHANGE) {
	305	if ( ctrl & NAND_CLE ) {
	306	hwctl \|= 0x1;
	307	writeb(0x00, (this->IO_ADDR_W + 0x0a));
	308	} else {
	309	hwctl &= ~0x1;
	310	writeb(0x00, (this->IO_ADDR_W + 0x08));
	311	}
	312	if ( ctrl & NAND_ALE ) {
	313	hwctl \|= 0x2;
	314	writeb(0x00, (this->IO_ADDR_W + 0x09));
	315	} else {
	316	hwctl &= ~0x2;
	317	writeb(0x00, (this->IO_ADDR_W + 0x08));
	318	}
	319	if ( (ctrl & NAND_NCE) != NAND_NCE)
	320	writeb(0x00, (this->IO_ADDR_W + 0x0c));
	321	else
	322	writeb(0x00, (this->IO_ADDR_W + 0x08));
	323	}
	324	if (cmd != NAND_CMD_NONE)
	325	writeb(cmd, this->IO_ADDR_W);
	326
	327	}
9dd41a7b	328
28afe016	329	static u_char ids_nand_read_byte(struct mtd_info *mtd)
9dd41a7b	330	{
28afe016	331	struct nand_chip *this = mtd->priv;
9dd41a7b	332
28afe016 HS	333	return readb(this->IO_ADDR_R);
	334	}
	335
	336	static void ids_nand_write_buf(struct mtd_info mtd, const u_char buf, int len)
	337	{
	338	struct nand_chip *nand = mtd->priv;
	339	int i;
	340
	341	for (i = 0; i < len; i++) {
	342	if (hwctl & 0x1)
	343	writeb(buf[i], (nand->IO_ADDR_W + 0x02));
	344	else if (hwctl & 0x2)
	345	writeb(buf[i], (nand->IO_ADDR_W + 0x01));
	346	else
	347	writeb(buf[i], nand->IO_ADDR_W);
	348	}
	349	}
9dd41a7b	350
28afe016 HS	351	static void ids_nand_read_buf(struct mtd_info mtd, u_char buf, int len)
	352	{
	353	struct nand_chip *this = mtd->priv;
	354	int i;
	355
	356	for (i = 0; i < len; i++) {
	357	buf[i] = readb(this->IO_ADDR_R);
	358	}
	359	}
	360
	361	static int ids_nand_dev_ready(struct mtd_info *mtd)
	362	{
	363	/* constant delay (see also tR in the datasheet) */
	364	udelay(12);
	365	return 1;
	366	}
	367
	368	int board_nand_init(struct nand_chip *nand)
	369	{
	370	nand->ecc.mode = NAND_ECC_SOFT;
	371
	372	/* Reference hardware control function */
	373	nand->cmd_ctrl = ids_nand_hwctrl;
	374	nand->read_byte = ids_nand_read_byte;
	375	nand->write_buf = ids_nand_write_buf;
	376	nand->read_buf = ids_nand_read_buf;
	377	nand->dev_ready = ids_nand_dev_ready;
	378	nand->chip_delay = 12;
	379
	380	return 0;
9dd41a7b WD	381	}
9dd41a7b WD	382
f2302d44	383	#endif /* CONFIG_CMD_NAND */
6abd82e1 SS	384
6abd82e1 SS	385	#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
6abd82e1 SS	386	void ft_board_setup(void blob, bd_t bd)
	387	{
	388	ft_cpu_setup( blob, bd);
6abd82e1 SS	389	}
6abd82e1 SS	390	#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */