projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5a4dcfac GJ |
1 | /* |
| 2 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> | |
| 3 | * | |
| 0b17998e | 4 | * SPDX-License-Identifier: GPL-2.0 |
| 5a4dcfac GJ |
5 | */ |
| 6 | ||
| ac12984d GJ |
7 | #include <config.h> |
| 8 | #include <gt64120.h> | |
| baf37f06 PB |
9 | #include <msc01.h> |
| 10 | #include <pci.h> | |
| ac12984d GJ |
11 | |
| 12 | #include <asm/addrspace.h> | |
| 5a4dcfac | 13 | #include <asm/regdef.h> |
| ac12984d | 14 | #include <asm/malta.h> |
| e174bd74 | 15 | #include <asm/mipsregs.h> |
| ac12984d GJ |
16 | |
| 17 | #ifdef CONFIG_SYS_BIG_ENDIAN | |
| 18 | #define CPU_TO_GT32(_x) ((_x)) | |
| 19 | #else | |
| 20 | #define CPU_TO_GT32(_x) ( \ | |
| 21 | (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ | |
| 22 | (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) | |
| 23 | #endif | |
| 5a4dcfac GJ |
24 | |
| 25 | .text | |
| 26 | .set noreorder | |
| 27 | .set mips32 | |
| 28 | ||
| 29 | .globl lowlevel_init | |
| 30 | lowlevel_init: | |
| e174bd74 PB |
31 | /* disable any L2 cache for now */ |
| 32 | sync | |
| 33 | mfc0 t0, CP0_CONFIG, 2 | |
| 34 | ori t0, t0, 0x1 << 12 | |
| 35 | mtc0 t0, CP0_CONFIG, 2 | |
| 36 | ||
| baf37f06 PB |
37 | /* detect the core card */ |
| 38 | li t0, KSEG1ADDR(MALTA_REVISION) | |
| 39 | lw t0, 0(t0) | |
| 40 | srl t0, t0, MALTA_REVISION_CORID_SHF | |
| 41 | andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ | |
| 42 | MALTA_REVISION_CORID_SHF) | |
| 43 | ||
| 44 | /* core cards using the gt64120 system controller */ | |
| 45 | li t1, MALTA_REVISION_CORID_CORE_LV | |
| 46 | beq t0, t1, _gt64120 | |
| 47 | ||
| 48 | /* core cards using the MSC01 system controller */ | |
| 49 | li t1, MALTA_REVISION_CORID_CORE_FPGA6 | |
| 50 | beq t0, t1, _msc01 | |
| 51 | nop | |
| 52 | ||
| 53 | /* unknown system controller */ | |
| 54 | b . | |
| 55 | nop | |
| 5a4dcfac | 56 | |
| ac12984d GJ |
57 | /* |
| 58 | * Load BAR registers of GT64120 as done by YAMON | |
| 59 | * | |
| 60 | * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com> | |
| 61 | * to the barebox mailing list. | |
| 62 | * The subject of the original patch: | |
| 63 | * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' | |
| 64 | * URL: | |
| 65 | * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html | |
| 66 | * | |
| 67 | * based on write_bootloader() in qemu.git/hw/mips_malta.c | |
| 68 | * see GT64120 manual and qemu.git/hw/gt64xxx.c for details | |
| 69 | */ | |
| baf37f06 | 70 | _gt64120: |
| ac12984d GJ |
71 | /* move GT64120 registers from 0x14000000 to 0x1be00000 */ |
| 72 | li t1, KSEG1ADDR(GT_DEF_BASE) | |
| 73 | li t0, CPU_TO_GT32(0xdf000000) | |
| 74 | sw t0, GT_ISD_OFS(t1) | |
| 75 | ||
| 76 | /* setup MEM-to-PCI0 mapping */ | |
| 77 | li t1, KSEG1ADDR(MALTA_GT_BASE) | |
| 78 | ||
| 79 | /* setup PCI0 io window to 0x18000000-0x181fffff */ | |
| 80 | li t0, CPU_TO_GT32(0xc0000000) | |
| 81 | sw t0, GT_PCI0IOLD_OFS(t1) | |
| 82 | li t0, CPU_TO_GT32(0x40000000) | |
| 83 | sw t0, GT_PCI0IOHD_OFS(t1) | |
| 84 | ||
| 85 | /* setup PCI0 mem windows */ | |
| 86 | li t0, CPU_TO_GT32(0x80000000) | |
| 87 | sw t0, GT_PCI0M0LD_OFS(t1) | |
| 88 | li t0, CPU_TO_GT32(0x3f000000) | |
| 89 | sw t0, GT_PCI0M0HD_OFS(t1) | |
| 90 | ||
| 91 | li t0, CPU_TO_GT32(0xc1000000) | |
| 92 | sw t0, GT_PCI0M1LD_OFS(t1) | |
| 93 | li t0, CPU_TO_GT32(0x5e000000) | |
| 94 | sw t0, GT_PCI0M1HD_OFS(t1) | |
| 95 | ||
| 5a4dcfac GJ |
96 | jr ra |
| 97 | nop | |
| baf37f06 PB |
98 | |
| 99 | /* | |
| 100 | * | |
| 101 | */ | |
| 102 | _msc01: | |
| 103 | /* setup peripheral bus controller clock divide */ | |
| 104 | li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE) | |
| 105 | li t1, 0x1 << MSC01_PBC_CLKCFG_SHF | |
| 106 | sw t1, MSC01_PBC_CLKCFG_OFS(t0) | |
| 107 | ||
| 108 | /* tweak peripheral bus controller timings */ | |
| 109 | li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \ | |
| 110 | (0x1 << MSC01_PBC_CS0TIM_CAT_SHF) | |
| 111 | sw t1, MSC01_PBC_CS0TIM_OFS(t0) | |
| 112 | li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \ | |
| 113 | (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \ | |
| 114 | (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \ | |
| 115 | (0x2 << MSC01_PBC_CS0RW_WAT_SHF) | |
| 116 | sw t1, MSC01_PBC_CS0RW_OFS(t0) | |
| 117 | lw t1, MSC01_PBC_CS0CFG_OFS(t0) | |
| 118 | li t2, MSC01_PBC_CS0CFG_DTYP_MSK | |
| 119 | and t1, t2 | |
| 120 | ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \ | |
| 121 | (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \ | |
| 122 | (0x10 << MSC01_PBC_CS0CFG_WS_SHF) | |
| 123 | sw t1, MSC01_PBC_CS0CFG_OFS(t0) | |
| 124 | ||
| 125 | /* setup basic address decode */ | |
| 126 | li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE) | |
| 127 | li t1, 0x0 | |
| 128 | li t2, -CONFIG_SYS_MEM_SIZE | |
| 129 | sw t1, MSC01_BIU_MCBAS1L_OFS(t0) | |
| 130 | sw t2, MSC01_BIU_MCMSK1L_OFS(t0) | |
| 131 | sw t1, MSC01_BIU_MCBAS2L_OFS(t0) | |
| 132 | sw t2, MSC01_BIU_MCMSK2L_OFS(t0) | |
| 133 | ||
| 134 | /* initialise IP1 - unused */ | |
| 135 | li t1, MALTA_MSC01_IP1_BASE | |
| 136 | li t2, -MALTA_MSC01_IP1_SIZE | |
| 137 | sw t1, MSC01_BIU_IP1BAS1L_OFS(t0) | |
| 138 | sw t2, MSC01_BIU_IP1MSK1L_OFS(t0) | |
| 139 | sw t1, MSC01_BIU_IP1BAS2L_OFS(t0) | |
| 140 | sw t2, MSC01_BIU_IP1MSK2L_OFS(t0) | |
| 141 | ||
| 142 | /* initialise IP2 - PCI */ | |
| 143 | li t1, MALTA_MSC01_IP2_BASE1 | |
| 144 | li t2, -MALTA_MSC01_IP2_SIZE1 | |
| 145 | sw t1, MSC01_BIU_IP2BAS1L_OFS(t0) | |
| 146 | sw t2, MSC01_BIU_IP2MSK1L_OFS(t0) | |
| 147 | li t1, MALTA_MSC01_IP2_BASE2 | |
| 148 | li t2, -MALTA_MSC01_IP2_SIZE2 | |
| 149 | sw t1, MSC01_BIU_IP2BAS2L_OFS(t0) | |
| 150 | sw t2, MSC01_BIU_IP2MSK2L_OFS(t0) | |
| 151 | ||
| 152 | /* initialise IP3 - peripheral bus controller */ | |
| 153 | li t1, MALTA_MSC01_IP3_BASE | |
| 154 | li t2, -MALTA_MSC01_IP3_SIZE | |
| 155 | sw t1, MSC01_BIU_IP3BAS1L_OFS(t0) | |
| 156 | sw t2, MSC01_BIU_IP3MSK1L_OFS(t0) | |
| 157 | sw t1, MSC01_BIU_IP3BAS2L_OFS(t0) | |
| 158 | sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) | |
| 159 | ||
| 160 | /* setup PCI memory */ | |
| 161 | li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE) | |
| 162 | li t1, MALTA_MSC01_PCIMEM_BASE | |
| 163 | li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK | |
| 164 | li t3, MALTA_MSC01_PCIMEM_MAP | |
| 165 | sw t1, MSC01_PCI_SC2PMBASL_OFS(t0) | |
| 166 | sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0) | |
| 167 | sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0) | |
| 168 | ||
| 169 | /* setup PCI I/O */ | |
| 170 | li t1, MALTA_MSC01_PCIIO_BASE | |
| 171 | li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK | |
| 172 | li t3, MALTA_MSC01_PCIIO_MAP | |
| 173 | sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0) | |
| 174 | sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0) | |
| 175 | sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) | |
| 176 | ||
| 177 | /* setup PCI_BAR0 memory window */ | |
| 178 | li t1, -CONFIG_SYS_MEM_SIZE | |
| 179 | sw t1, MSC01_PCI_BAR0_OFS(t0) | |
| 180 | ||
| 181 | /* setup PCI to SysCon/CPU translation */ | |
| 182 | sw t1, MSC01_PCI_P2SCMSKL_OFS(t0) | |
| 183 | sw zero, MSC01_PCI_P2SCMAPL_OFS(t0) | |
| 184 | ||
| 185 | /* setup PCI vendor & device IDs */ | |
| 186 | li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \ | |
| 187 | (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF) | |
| 188 | sw t1, MSC01_PCI_HEAD0_OFS(t0) | |
| 189 | ||
| 190 | /* setup PCI subsystem vendor & device IDs */ | |
| 191 | sw t1, MSC01_PCI_HEAD11_OFS(t0) | |
| 192 | ||
| 193 | /* setup PCI class, revision */ | |
| 194 | li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \ | |
| 195 | (0x1 << MSC01_PCI_HEAD2_REV_SHF) | |
| 196 | sw t1, MSC01_PCI_HEAD2_OFS(t0) | |
| 197 | ||
| 198 | /* ensure a sane setup */ | |
| 199 | sw zero, MSC01_PCI_HEAD3_OFS(t0) | |
| 200 | sw zero, MSC01_PCI_HEAD4_OFS(t0) | |
| 201 | sw zero, MSC01_PCI_HEAD5_OFS(t0) | |
| 202 | sw zero, MSC01_PCI_HEAD6_OFS(t0) | |
| 203 | sw zero, MSC01_PCI_HEAD7_OFS(t0) | |
| 204 | sw zero, MSC01_PCI_HEAD8_OFS(t0) | |
| 205 | sw zero, MSC01_PCI_HEAD9_OFS(t0) | |
| 206 | sw zero, MSC01_PCI_HEAD10_OFS(t0) | |
| 207 | sw zero, MSC01_PCI_HEAD12_OFS(t0) | |
| 208 | sw zero, MSC01_PCI_HEAD13_OFS(t0) | |
| 209 | sw zero, MSC01_PCI_HEAD14_OFS(t0) | |
| 210 | sw zero, MSC01_PCI_HEAD15_OFS(t0) | |
| 211 | ||
| 212 | /* setup PCI command register */ | |
| 213 | li t1, (PCI_COMMAND_FAST_BACK | \ | |
| 214 | PCI_COMMAND_SERR | \ | |
| 215 | PCI_COMMAND_PARITY | \ | |
| 216 | PCI_COMMAND_MASTER | \ | |
| 217 | PCI_COMMAND_MEMORY) | |
| 218 | sw t1, MSC01_PCI_HEAD1_OFS(t0) | |
| 219 | ||
| 220 | /* setup PCI byte swapping */ | |
| 221 | #ifdef CONFIG_SYS_BIG_ENDIAN | |
| 222 | li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \ | |
| 223 | (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF) | |
| 224 | sw t1, MSC01_PCI_SWAP_OFS(t0) | |
| 225 | #else | |
| 226 | sw zero, MSC01_PCI_SWAP_OFS(t0) | |
| 227 | #endif | |
| 228 | ||
| 229 | /* enable PCI host configuration cycles */ | |
| 230 | lw t1, MSC01_PCI_CFG_OFS(t0) | |
| 231 | li t2, MSC01_PCI_CFG_RA_MSK | \ | |
| 232 | MSC01_PCI_CFG_G_MSK | \ | |
| 233 | MSC01_PCI_CFG_EN_MSK | |
| 234 | or t1, t1, t2 | |
| 235 | sw t1, MSC01_PCI_CFG_OFS(t0) | |
| 236 | ||
| 237 | jr ra | |
| 238 | nop |