[people/ms/u-boot.git] / board / imgtec / malta / malta.c

/*
 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2013 Imagination Technologies
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <netdev.h>
#include <pci.h>
#include <pci_gt64120.h>
#include <pci_msc01.h>
#include <rtc.h>
#include <serial.h>

#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/malta.h>

#include "superio.h"

enum core_card {
	CORE_UNKNOWN,
	CORE_LV,
	CORE_FPGA6,
};

enum sys_con {
	SYSCON_UNKNOWN,
	SYSCON_GT64120,
	SYSCON_MSC01,
};

static void malta_lcd_puts(const char *str)
{
	int i;
	void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);

	/* print up to 8 characters of the string */
	for (i = 0; i < min(strlen(str), 8); i++) {
		__raw_writel(str[i], reg);
		reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
	}

	/* fill the rest of the display with spaces */
	for (; i < 8; i++) {
		__raw_writel(' ', reg);
		reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
	}
}

static enum core_card malta_core_card(void)
{
	u32 corid, rev;

	rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
	corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;

	switch (corid) {
	case MALTA_REVISION_CORID_CORE_LV:
		return CORE_LV;

	case MALTA_REVISION_CORID_CORE_FPGA6:
		return CORE_FPGA6;

	default:
		return CORE_UNKNOWN;
	}
}

static enum sys_con malta_sys_con(void)
{
	switch (malta_core_card()) {
	case CORE_LV:
		return SYSCON_GT64120;

	case CORE_FPGA6:
		return SYSCON_MSC01;

	default:
		return SYSCON_UNKNOWN;
	}
}

phys_size_t initdram(int board_type)
{
	return CONFIG_SYS_MEM_SIZE;
}

int checkboard(void)
{
	enum core_card core;

	malta_lcd_puts("U-boot");
	puts("Board: MIPS Malta");

	core = malta_core_card();
	switch (core) {
	case CORE_LV:
		puts(" CoreLV");
		break;

	case CORE_FPGA6:
		puts(" CoreFPGA6");
		break;

	default:
		puts(" CoreUnknown");
	}

	putc('\n');
	return 0;
}

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}

void _machine_restart(void)
{
	void __iomem *reset_base;

	reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
	__raw_writel(GORESET, reset_base);
}

int board_early_init_f(void)
{
	void *io_base;

	/* choose correct PCI I/O base */
	switch (malta_sys_con()) {
	case SYSCON_GT64120:
		io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
		break;

	case SYSCON_MSC01:
		io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
		break;

	default:
		return -1;
	}

	/* setup FDC37M817 super I/O controller */
	malta_superio_init(io_base);

	return 0;
}

int misc_init_r(void)
{
	rtc_reset();

	return 0;
}

struct serial_device *default_serial_console(void)
{
	switch (malta_sys_con()) {
	case SYSCON_GT64120:
		return &eserial1_device;

	default:
	case SYSCON_MSC01:
		return &eserial2_device;
	}
}

void pci_init_board(void)
{
	pci_dev_t bdf;
	u32 val32;
	u8 val8;

	switch (malta_sys_con()) {
	case SYSCON_GT64120:
		set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));

		gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
				 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
				 0x10000000, 0x10000000, 128 * 1024 * 1024,
				 0x00000000, 0x00000000, 0x20000);
		break;

	default:
	case SYSCON_MSC01:
		set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));

		msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
			       0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
			       MALTA_MSC01_PCIMEM_MAP,
			       CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
			       MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
			       0x00000000, MALTA_MSC01_PCIIO_SIZE);
		break;
	}

	bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
			      PCI_DEVICE_ID_INTEL_82371AB_0, 0);
	if (bdf == -1)
		panic("Failed to find PIIX4 PCI bridge\n");

	/* setup PCI interrupt routing */
	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);

	/* mux SERIRQ onto SERIRQ pin */
	pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
	val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
	pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);

	/* enable SERIRQ - Linux currently depends upon this */
	pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
	val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
	pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
}
Commit	Line	Data
5a4dcfac GJ	1	/*
5a4dcfac GJ	2	* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
baf37f06	3	* Copyright (C) 2013 Imagination Technologies
5a4dcfac	4	*
0b17998e	5	* SPDX-License-Identifier: GPL-2.0
5a4dcfac GJ	6	*/
	7
	8	#include <common.h>
f1957499	9	#include <netdev.h>
81f98bbd	10	#include <pci.h>
baf37f06 PB	11	#include <pci_gt64120.h>
baf37f06 PB	12	#include <pci_msc01.h>
3ced12a0	13	#include <rtc.h>
baf37f06	14	#include <serial.h>
5a4dcfac	15
feaa6066	16	#include <asm/addrspace.h>
01564315 GJ	17	#include <asm/io.h>
	18	#include <asm/malta.h>
	19
a257f626 PB	20	#include "superio.h"
a257f626 PB	21
baf37f06 PB	22	enum core_card {
	23	CORE_UNKNOWN,
	24	CORE_LV,
	25	CORE_FPGA6,
	26	};
	27
	28	enum sys_con {
	29	SYSCON_UNKNOWN,
	30	SYSCON_GT64120,
	31	SYSCON_MSC01,
	32	};
	33
e0ada631 PB	34	static void malta_lcd_puts(const char *str)
	35	{
	36	int i;
	37	void reg = (void )CKSEG1ADDR(MALTA_ASCIIPOS0);
	38
	39	/* print up to 8 characters of the string */
	40	for (i = 0; i < min(strlen(str), 8); i++) {
	41	__raw_writel(str[i], reg);
	42	reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
	43	}
	44
	45	/* fill the rest of the display with spaces */
	46	for (; i < 8; i++) {
	47	__raw_writel(' ', reg);
	48	reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
	49	}
	50	}
	51
baf37f06 PB	52	static enum core_card malta_core_card(void)
	53	{
	54	u32 corid, rev;
	55
	56	rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
	57	corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
	58
	59	switch (corid) {
	60	case MALTA_REVISION_CORID_CORE_LV:
	61	return CORE_LV;
	62
	63	case MALTA_REVISION_CORID_CORE_FPGA6:
	64	return CORE_FPGA6;
	65
	66	default:
	67	return CORE_UNKNOWN;
	68	}
	69	}
	70
	71	static enum sys_con malta_sys_con(void)
	72	{
	73	switch (malta_core_card()) {
	74	case CORE_LV:
	75	return SYSCON_GT64120;
	76
	77	case CORE_FPGA6:
	78	return SYSCON_MSC01;
	79
	80	default:
	81	return SYSCON_UNKNOWN;
	82	}
	83	}
	84
5a4dcfac GJ	85	phys_size_t initdram(int board_type)
	86	{
	87	return CONFIG_SYS_MEM_SIZE;
	88	}
	89
	90	int checkboard(void)
	91	{
baf37f06 PB	92	enum core_card core;
baf37f06 PB	93
e0ada631	94	malta_lcd_puts("U-boot");
baf37f06 PB	95	puts("Board: MIPS Malta");
	96
	97	core = malta_core_card();
	98	switch (core) {
	99	case CORE_LV:
	100	puts(" CoreLV");
	101	break;
	102
	103	case CORE_FPGA6:
	104	puts(" CoreFPGA6");
	105	break;
	106
	107	default:
	108	puts(" CoreUnknown");
	109	}
	110
	111	putc('\n');
5a4dcfac GJ	112	return 0;
5a4dcfac GJ	113	}
01564315	114
f1957499 GJ	115	int board_eth_init(bd_t *bis)
	116	{
	117	return pci_eth_init(bis);
	118	}
	119
01564315 GJ	120	void _machine_restart(void)
	121	{
	122	void __iomem *reset_base;
	123
	124	reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
	125	__raw_writel(GORESET, reset_base);
	126	}
feaa6066	127
a257f626 PB	128	int board_early_init_f(void)
a257f626 PB	129	{
baf37f06 PB	130	void *io_base;
	131
	132	/* choose correct PCI I/O base */
	133	switch (malta_sys_con()) {
	134	case SYSCON_GT64120:
	135	io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
	136	break;
	137
	138	case SYSCON_MSC01:
	139	io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
	140	break;
	141
	142	default:
	143	return -1;
	144	}
	145
a257f626	146	/* setup FDC37M817 super I/O controller */
baf37f06	147	malta_superio_init(io_base);
a257f626 PB	148
	149	return 0;
	150	}
	151
3ced12a0 PB	152	int misc_init_r(void)
	153	{
	154	rtc_reset();
	155
	156	return 0;
	157	}
	158
baf37f06 PB	159	struct serial_device *default_serial_console(void)
	160	{
	161	switch (malta_sys_con()) {
	162	case SYSCON_GT64120:
	163	return &eserial1_device;
	164
	165	default:
	166	case SYSCON_MSC01:
	167	return &eserial2_device;
	168	}
	169	}
	170
feaa6066 GJ	171	void pci_init_board(void)
feaa6066 GJ	172	{
81f98bbd	173	pci_dev_t bdf;
bea12b78 PB	174	u32 val32;
bea12b78 PB	175	u8 val8;
81f98bbd	176
baf37f06 PB	177	switch (malta_sys_con()) {
	178	case SYSCON_GT64120:
	179	set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
	180
	181	gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
	182	0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
	183	0x10000000, 0x10000000, 128 * 1024 * 1024,
	184	0x00000000, 0x00000000, 0x20000);
	185	break;
	186
	187	default:
	188	case SYSCON_MSC01:
	189	set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
feaa6066	190
baf37f06 PB	191	msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
	192	0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
	193	MALTA_MSC01_PCIMEM_MAP,
	194	CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
	195	MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
	196	0x00000000, MALTA_MSC01_PCIIO_SIZE);
	197	break;
	198	}
81f98bbd PB	199
	200	bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
	201	PCI_DEVICE_ID_INTEL_82371AB_0, 0);
	202	if (bdf == -1)
	203	panic("Failed to find PIIX4 PCI bridge\n");
	204
	205	/* setup PCI interrupt routing */
	206	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
	207	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
	208	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
	209	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
bea12b78 PB	210
	211	/* mux SERIRQ onto SERIRQ pin */
	212	pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
	213	val32 \|= PCI_CFG_PIIX4_GENCFG_SERIRQ;
	214	pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
	215
	216	/* enable SERIRQ - Linux currently depends upon this */
	217	pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
	218	val8 \|= PCI_CFG_PIIX4_SERIRQC_EN \| PCI_CFG_PIIX4_SERIRQC_CONT;
	219	pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
feaa6066	220	}