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5ad86216 SH |
1 | /* |
2 | * | |
3 | * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | #include <common.h> | |
a2bb7105 | 26 | #include <s6e63d6.h> |
5ad86216 SH |
27 | #include <asm/arch/mx31.h> |
28 | #include <asm/arch/mx31-regs.h> | |
29 | ||
30 | DECLARE_GLOBAL_DATA_PTR; | |
31 | ||
32 | int dram_init (void) | |
33 | { | |
34 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
35 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
36 | ||
37 | return 0; | |
38 | } | |
39 | ||
40 | int board_init (void) | |
41 | { | |
42 | __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ | |
43 | __REG(CSCR_L(0)) = 0x10000d03; | |
44 | __REG(CSCR_A(0)) = 0x00720900; | |
45 | ||
46 | __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */ | |
47 | __REG(CSCR_L(1)) = 0x444a4541; | |
48 | __REG(CSCR_A(1)) = 0x44443302; | |
49 | ||
50 | __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */ | |
51 | __REG(CSCR_L(4)) = 0x22252521; | |
52 | __REG(CSCR_A(4)) = 0x22220a00; | |
53 | ||
54 | /* setup pins for UART1 */ | |
55 | mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); | |
56 | mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); | |
57 | mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); | |
b6b183c5 | 58 | mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); |
5ad86216 SH |
59 | |
60 | /* setup pins for I2C2 (for EEPROM, RTC) */ | |
61 | mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); | |
b6b183c5 | 62 | mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); |
5ad86216 | 63 | |
890a017a DZ |
64 | gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ |
65 | gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ | |
5ad86216 SH |
66 | |
67 | return 0; | |
68 | } | |
69 | ||
a2bb7105 GL |
70 | #ifdef BOARD_LATE_INIT |
71 | int board_late_init(void) | |
72 | { | |
73 | #ifdef CONFIG_S6E63D6 | |
74 | struct s6e63d6 data = { | |
75 | /* | |
76 | * See comment in mxc_spi.c::decode_cs() for .cs field format. | |
77 | * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect | |
78 | * 2 of the SPI controller #1, since it is unused. | |
79 | */ | |
80 | .cs = 2 | (57 << 8), | |
81 | .bus = 0, | |
82 | .id = 0, | |
83 | }; | |
84 | int ret; | |
85 | ||
86 | /* SPI1 */ | |
87 | mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); | |
88 | mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); | |
89 | mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); | |
90 | mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); | |
91 | mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); | |
92 | mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); | |
93 | mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); | |
94 | ||
95 | /* start SPI1 clock */ | |
96 | __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); | |
97 | ||
98 | /* GPIO 57 */ | |
99 | /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ | |
100 | mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); | |
101 | ||
102 | /* SPI1 CS2 is free */ | |
103 | ret = s6e63d6_init(&data); | |
104 | if (ret) | |
105 | return ret; | |
106 | ||
107 | /* | |
108 | * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC | |
109 | * OLED display connected to a S6E63D6 SPI display controller in the | |
110 | * 18 bit RGB mode | |
111 | */ | |
112 | s6e63d6_index(&data, 2); | |
113 | s6e63d6_param(&data, 0x0182); | |
114 | s6e63d6_index(&data, 3); | |
115 | s6e63d6_param(&data, 0x8130); | |
116 | s6e63d6_index(&data, 0x10); | |
117 | s6e63d6_param(&data, 0x0000); | |
118 | s6e63d6_index(&data, 5); | |
119 | s6e63d6_param(&data, 0x0001); | |
120 | s6e63d6_index(&data, 0x22); | |
121 | #endif | |
122 | return 0; | |
123 | } | |
124 | #endif | |
125 | ||
5ad86216 SH |
126 | int checkboard (void) |
127 | { | |
128 | printf("Board: Phytec phyCore i.MX31\n"); | |
129 | return 0; | |
130 | } |