[people/ms/u-boot.git] / board / incaip / memsetup.S

/*
 *  Memory sub-system initialization code for INCA-IP development board.
 *
 *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/regdef.h>


#define EBU_MODUL_BASE          0xB8000200
#define EBU_CLC(value)          0x0000(value)
#define EBU_CON(value)          0x0010(value)
#define EBU_ADDSEL0(value)      0x0020(value)
#define EBU_ADDSEL1(value)      0x0024(value)
#define EBU_ADDSEL2(value)      0x0028(value)
#define EBU_BUSCON0(value)      0x0060(value)
#define EBU_BUSCON1(value)      0x0064(value)
#define EBU_BUSCON2(value)      0x0068(value)

#define MC_MODUL_BASE           0xBF800000
#define MC_ERRCAUSE(value)      0x0100(value)
#define MC_ERRADDR(value)       0x0108(value)
#define MC_IOGP(value)          0x0800(value)
#define MC_SELFRFSH(value)      0x0A00(value)
#define MC_CTRLENA(value)       0x1000(value)
#define MC_MRSCODE(value)       0x1008(value)
#define MC_CFGDW(value)         0x1010(value)
#define MC_CFGPB0(value)        0x1018(value)
#define MC_LATENCY(value)       0x1038(value)
#define MC_TREFRESH(value)      0x1040(value)

#define CGU_MODUL_BASE          0xBF107000
#define CGU_PLL1CR(value)       0x0008(value)
#define CGU_DIVCR(value)        0x0010(value)
#define CGU_MUXCR(value)        0x0014(value)
#define CGU_PLL1SR(value)       0x000C(value)

	.set	noreorder		


/*
 * void ebu_init(long)
 *
 * a0 has the clock value we are going to run at
 */
	.globl	ebu_init
	.ent	ebu_init
ebu_init:

	li	t1, EBU_MODUL_BASE
	li	t2, 0xA0000041
	sw	t2, EBU_ADDSEL0(t1)
	li	t2, 0xA0800041
	sw	t2, EBU_ADDSEL2(t1)
	li	t2, 0xBE0000F1
	sw	t2, EBU_ADDSEL1(t1)

	li	t3, 100000000
	beq	a0, t3, 1f
	nop
	li	t3, 133000000
	beq	a0, t3, 2f
	nop
	li	t3, 150000000
	beq	a0, t3, 2f
	nop
	b	3f
	nop

	/* 100 MHz */
1:
	li	t2, 0x8841417D
	sw	t2, EBU_BUSCON0(t1)
	sw	t2, EBU_BUSCON2(t1)
	li	t2, 0x684142BD
	b	3f
	sw	t2, EBU_BUSCON1(t1)	/* delay slot */

	/* 133 or 150 MHz */
2:
	li	t2, 0x8841417E
	sw	t2, EBU_BUSCON0(t1)
	sw	t2, EBU_BUSCON2(t1)
	li	t2, 0x684143FD
	sw	t2, EBU_BUSCON1(t1)
3:
	j	ra
	nop

	.end	ebu_init


/*
 * void cgu_init(long)
 *
 * a0 has the clock value
 */
	.globl	cgu_init
	.ent	cgu_init
cgu_init:

	li	t1, CGU_MODUL_BASE

	li	t3, 100000000
	beq	a0, t3, 1f
	nop
	li	t3, 133000000
	beq	a0, t3, 2f
	nop
	li	t3, 150000000
	beq	a0, t3, 3f
	nop
	b	5f
	nop

	/* 100 MHz clock */
1:
	li	t2, 0x80000014
	sw	t2, CGU_DIVCR(t1)
	li	t2, 0x80000000
	sw	t2, CGU_MUXCR(t1)
	li	t2, 0x800B0001
	b	5f
	sw	t2, CGU_PLL1CR(t1)	/* delay slot */

	/* 133 MHz clock */
2:
	li	t2, 0x80000054
	sw	t2, CGU_DIVCR(t1)
	li	t2, 0x80000000
	sw	t2, CGU_MUXCR(t1)
	li	t2, 0x800B0001
	b	5f
	sw	t2, CGU_PLL1CR(t1)	/* delay slot */

	/* 150 MHz clock */
3:
	li	t2, 0x80000017
	sw	t2, CGU_DIVCR(t1)
	li	t2, 0xC00B0001
	sw	t2, CGU_PLL1CR(t1)
	li	t3, 0x80000000
4:
	lw	t2, CGU_PLL1SR(t1)
	and	t2, t2, t3
	beq	t2, zero, 4b
	nop
	li	t2, 0x80000001
	sw	t2, CGU_MUXCR(t1)
5:
	j	ra
	nop

	.end	cgu_init


	.globl	memsetup
	.ent	memsetup
memsetup:

	/* EBU and CGU Initialization.
	 */
	li	a0, CPU_CLOCK_RATE
	move	t0, ra

	/* We rely on the fact that neither ebu_init() nor cgu_init()
	 * modify t0 and a0.
	 */
	bal	ebu_init
	nop
	bal	cgu_init
	nop
	move	ra, t0

	/* SDRAM Initialization.
	 */
	li	t0, MC_MODUL_BASE

	/* Clear Error log registers */
	sw	zero, MC_ERRCAUSE(t0)
	sw	zero, MC_ERRADDR(t0)

	/* Set clock ratio to 1:1 */
	li	t1, 0x03		/* clkrat=1:1, rddel=3 */
	sw	t1, MC_IOGP(t0)

	/* Clear Power-down registers */
	sw	zero, MC_SELFRFSH(t0)

	/* Set CAS Latency */
	li	t1, 0x00000020		/* CL = 2 */
	sw	t1, MC_MRSCODE(t0)

	/* Set word width to 16 bit */
	li	t1, 0x2
	sw	t1, MC_CFGDW(t0)

	/* Set CS0 to SDRAM parameters */
	li	t1, 0x000014C9
	sw	t1, MC_CFGPB0(t0)

	/* Set SDRAM latency parameters */
	li	t1, 0x00026325		/* BC PC100 */
	sw	t1, MC_LATENCY(t0)

	/* Set SDRAM refresh rate */
	li	t1, 0x00000C30		/* 4K/64ms @ 100MHz */
	sw	t1, MC_TREFRESH(t0)

	/* Finally enable the controller */
	li	t1, 1
	sw	t1, MC_CTRLENA(t0)

	j	ra
	nop
	.end	memsetup
Commit	Line	Data
c021880a WD	1	/*
	2	* Memory sub-system initialization code for INCA-IP development board.
	3	*
	4	* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <config.h>
	26	#include <version.h>
	27	#include <asm/regdef.h>
	28
	29
	30	#define EBU_MODUL_BASE 0xB8000200
	31	#define EBU_CLC(value) 0x0000(value)
	32	#define EBU_CON(value) 0x0010(value)
	33	#define EBU_ADDSEL0(value) 0x0020(value)
	34	#define EBU_ADDSEL1(value) 0x0024(value)
	35	#define EBU_ADDSEL2(value) 0x0028(value)
	36	#define EBU_BUSCON0(value) 0x0060(value)
	37	#define EBU_BUSCON1(value) 0x0064(value)
	38	#define EBU_BUSCON2(value) 0x0068(value)
	39
	40	#define MC_MODUL_BASE 0xBF800000
	41	#define MC_ERRCAUSE(value) 0x0100(value)
	42	#define MC_ERRADDR(value) 0x0108(value)
	43	#define MC_IOGP(value) 0x0800(value)
	44	#define MC_SELFRFSH(value) 0x0A00(value)
	45	#define MC_CTRLENA(value) 0x1000(value)
	46	#define MC_MRSCODE(value) 0x1008(value)
	47	#define MC_CFGDW(value) 0x1010(value)
	48	#define MC_CFGPB0(value) 0x1018(value)
	49	#define MC_LATENCY(value) 0x1038(value)
	50	#define MC_TREFRESH(value) 0x1040(value)
	51
c021880a WD	52	#define CGU_MODUL_BASE 0xBF107000
	53	#define CGU_PLL1CR(value) 0x0008(value)
	54	#define CGU_DIVCR(value) 0x0010(value)
	55	#define CGU_MUXCR(value) 0x0014(value)
	56	#define CGU_PLL1SR(value) 0x000C(value)
c021880a	57
7cb22f97	58	.set noreorder
c021880a	59
c021880a	60
7cb22f97 WD	61	/*
	62	* void ebu_init(long)
	63	*
	64	* a0 has the clock value we are going to run at
	65	*/
	66	.globl ebu_init
	67	.ent ebu_init
	68	ebu_init:
	69
	70	li t1, EBU_MODUL_BASE
	71	li t2, 0xA0000041
	72	sw t2, EBU_ADDSEL0(t1)
	73	li t2, 0xA0800041
	74	sw t2, EBU_ADDSEL2(t1)
	75	li t2, 0xBE0000F1
	76	sw t2, EBU_ADDSEL1(t1)
	77
	78	li t3, 100000000
	79	beq a0, t3, 1f
	80	nop
	81	li t3, 133000000
	82	beq a0, t3, 2f
	83	nop
	84	li t3, 150000000
	85	beq a0, t3, 2f
	86	nop
	87	b 3f
	88	nop
c021880a	89
7cb22f97 WD	90	/* 100 MHz */
	91	1:
	92	li t2, 0x8841417D
	93	sw t2, EBU_BUSCON0(t1)
	94	sw t2, EBU_BUSCON2(t1)
	95	li t2, 0x684142BD
	96	b 3f
	97	sw t2, EBU_BUSCON1(t1) /* delay slot */
	98
	99	/* 133 or 150 MHz */
	100	2:
	101	li t2, 0x8841417E
	102	sw t2, EBU_BUSCON0(t1)
	103	sw t2, EBU_BUSCON2(t1)
	104	li t2, 0x684143FD
	105	sw t2, EBU_BUSCON1(t1)
	106	3:
	107	j ra
	108	nop
	109
	110	.end ebu_init
c021880a	111
c021880a	112
7cb22f97 WD	113	/*
	114	* void cgu_init(long)
	115	*
	116	* a0 has the clock value
	117	*/
	118	.globl cgu_init
	119	.ent cgu_init
	120	cgu_init:
	121
	122	li t1, CGU_MODUL_BASE
	123
	124	li t3, 100000000
	125	beq a0, t3, 1f
	126	nop
	127	li t3, 133000000
	128	beq a0, t3, 2f
	129	nop
	130	li t3, 150000000
	131	beq a0, t3, 3f
	132	nop
	133	b 5f
	134	nop
	135
	136	/* 100 MHz clock */
	137	1:
	138	li t2, 0x80000014
	139	sw t2, CGU_DIVCR(t1)
	140	li t2, 0x80000000
	141	sw t2, CGU_MUXCR(t1)
	142	li t2, 0x800B0001
	143	b 5f
	144	sw t2, CGU_PLL1CR(t1) /* delay slot */
	145
	146	/* 133 MHz clock */
	147	2:
	148	li t2, 0x80000054
	149	sw t2, CGU_DIVCR(t1)
	150	li t2, 0x80000000
	151	sw t2, CGU_MUXCR(t1)
	152	li t2, 0x800B0001
	153	b 5f
	154	sw t2, CGU_PLL1CR(t1) /* delay slot */
	155
	156	/* 150 MHz clock */
	157	3:
	158	li t2, 0x80000017
	159	sw t2, CGU_DIVCR(t1)
	160	li t2, 0xC00B0001
	161	sw t2, CGU_PLL1CR(t1)
	162	li t3, 0x80000000
	163	4:
	164	lw t2, CGU_PLL1SR(t1)
	165	and t2, t2, t3
	166	beq t2, zero, 4b
	167	nop
	168	li t2, 0x80000001
	169	sw t2, CGU_MUXCR(t1)
	170	5:
	171	j ra
	172	nop
	173
	174	.end cgu_init
	175
	176
177	.globl memsetup
178	.ent memsetup
179	memsetup:
180
181	/* EBU and CGU Initialization.
c021880a	182	*/
7cb22f97 WD	183	li a0, CPU_CLOCK_RATE
	184	move t0, ra
	185
	186	/* We rely on the fact that neither ebu_init() nor cgu_init()
	187	* modify t0 and a0.
	188	*/
	189	bal ebu_init
	190	nop
	191	bal cgu_init
	192	nop
	193	move ra, t0
c021880a WD	194
	195	/* SDRAM Initialization.
	196	*/
	197	li t0, MC_MODUL_BASE
	198
	199	/* Clear Error log registers */
	200	sw zero, MC_ERRCAUSE(t0)
	201	sw zero, MC_ERRADDR(t0)
	202
	203	/* Set clock ratio to 1:1 */
	204	li t1, 0x03 /* clkrat=1:1, rddel=3 */
	205	sw t1, MC_IOGP(t0)
	206
	207	/* Clear Power-down registers */
	208	sw zero, MC_SELFRFSH(t0)
	209
	210	/* Set CAS Latency */
	211	li t1, 0x00000020 /* CL = 2 */
	212	sw t1, MC_MRSCODE(t0)
	213
	214	/* Set word width to 16 bit */
8bde7f77	215	li t1, 0x2
c021880a WD	216	sw t1, MC_CFGDW(t0)
	217
	218	/* Set CS0 to SDRAM parameters */
	219	li t1, 0x000014C9
	220	sw t1, MC_CFGPB0(t0)
	221
	222	/* Set SDRAM latency parameters */
	223	li t1, 0x00026325 /* BC PC100 */
	224	sw t1, MC_LATENCY(t0)
	225
	226	/* Set SDRAM refresh rate */
	227	li t1, 0x00000C30 /* 4K/64ms @ 100MHz */
	228	sw t1, MC_TREFRESH(t0)
	229
	230	/* Finally enable the controller */
	231	li t1, 1
	232	sw t1, MC_CTRLENA(t0)
	233
	234	j ra
	235	nop
7cb22f97 WD	236	.end memsetup
7cb22f97 WD	237