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c021880a WD |
1 | /* |
2 | * Memory sub-system initialization code for INCA-IP development board. | |
3 | * | |
4 | * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <config.h> | |
26 | #include <version.h> | |
27 | #include <asm/regdef.h> | |
28 | ||
29 | ||
30 | #define EBU_MODUL_BASE 0xB8000200 | |
31 | #define EBU_CLC(value) 0x0000(value) | |
32 | #define EBU_CON(value) 0x0010(value) | |
33 | #define EBU_ADDSEL0(value) 0x0020(value) | |
34 | #define EBU_ADDSEL1(value) 0x0024(value) | |
35 | #define EBU_ADDSEL2(value) 0x0028(value) | |
36 | #define EBU_BUSCON0(value) 0x0060(value) | |
37 | #define EBU_BUSCON1(value) 0x0064(value) | |
38 | #define EBU_BUSCON2(value) 0x0068(value) | |
39 | ||
40 | #define MC_MODUL_BASE 0xBF800000 | |
41 | #define MC_ERRCAUSE(value) 0x0100(value) | |
42 | #define MC_ERRADDR(value) 0x0108(value) | |
43 | #define MC_IOGP(value) 0x0800(value) | |
44 | #define MC_SELFRFSH(value) 0x0A00(value) | |
45 | #define MC_CTRLENA(value) 0x1000(value) | |
46 | #define MC_MRSCODE(value) 0x1008(value) | |
47 | #define MC_CFGDW(value) 0x1010(value) | |
48 | #define MC_CFGPB0(value) 0x1018(value) | |
49 | #define MC_LATENCY(value) 0x1038(value) | |
50 | #define MC_TREFRESH(value) 0x1040(value) | |
51 | ||
c021880a WD |
52 | #define CGU_MODUL_BASE 0xBF107000 |
53 | #define CGU_PLL1CR(value) 0x0008(value) | |
54 | #define CGU_DIVCR(value) 0x0010(value) | |
55 | #define CGU_MUXCR(value) 0x0014(value) | |
56 | #define CGU_PLL1SR(value) 0x000C(value) | |
c021880a WD |
57 | |
58 | .globl memsetup | |
59 | memsetup: | |
60 | ||
61 | /* EBU Initialization for the Flash CS0 and CS2. | |
62 | */ | |
63 | li t0, EBU_MODUL_BASE | |
64 | ||
65 | li t1, 0xA0000041 | |
66 | sw t1, EBU_ADDSEL0(t0) | |
67 | ||
d791b1dc WD |
68 | #if CPU_CLOCK_RATE==100000000 /* 100 MHz clock for the MIPS core */ |
69 | lw t1, EBU_BUSCON0(t0) /* value set up by magic flash word */ | |
c021880a | 70 | sw t1, EBU_BUSCON2(t0) |
d791b1dc WD |
71 | #else /* 150 MHz or 133 MHz */ |
72 | li t1, 0x8841417E | |
73 | sw t1, EBU_BUSCON0(t0) | |
c021880a WD |
74 | sw t1, EBU_BUSCON2(t0) |
75 | #endif | |
76 | ||
77 | li t1, 0xA0800041 | |
78 | sw t1, EBU_ADDSEL2(t0) | |
79 | ||
80 | /* Need to initialize CS1 too, so as to to prevent overlapping with | |
81 | * Flash bank 1. | |
82 | */ | |
83 | li t1, 0xBE0000F1 | |
84 | sw t1, EBU_ADDSEL1(t0) | |
85 | ||
d791b1dc | 86 | #if CPU_CLOCK_RATE==100000000 /* 100 MHz clock for the MIPS core */ |
c021880a | 87 | li t1, 0x684142BD |
d791b1dc WD |
88 | #else /* 150 MHz or 133 MHz */ |
89 | li t1, 0x684143FD | |
c021880a WD |
90 | #endif |
91 | sw t1, EBU_BUSCON1(t0) | |
92 | ||
93 | #if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */ | |
94 | li t0, CGU_MODUL_BASE | |
95 | li t1, 0x80000017 | |
96 | sw t1, CGU_DIVCR(t0) | |
97 | li t1, 0xC00B0001 | |
98 | sw t1, CGU_PLL1CR(t0) | |
99 | lui t2, 0x8000 | |
100 | b1: | |
101 | lw t1, CGU_PLL1SR(t0) | |
102 | and t1, t1, t2 | |
103 | beq t1, zero, b1 | |
104 | li t1, 0x80000001 | |
105 | sw t1, CGU_MUXCR(t0) | |
d791b1dc WD |
106 | #elif CPU_CLOCK_RATE==133000000 /* 133 MHz clock for the MIPS core */ |
107 | li t0, CGU_MODUL_BASE | |
108 | li t1, 0x80000054 | |
109 | sw t1, CGU_DIVCR(t0) | |
110 | li t1, 0x80000000 | |
111 | sw t1, CGU_MUXCR(t0) | |
112 | li t1, 0x800B0001 | |
113 | sw t1, CGU_PLL1CR(t0) | |
c021880a WD |
114 | #endif |
115 | ||
116 | /* SDRAM Initialization. | |
117 | */ | |
118 | li t0, MC_MODUL_BASE | |
119 | ||
120 | /* Clear Error log registers */ | |
121 | sw zero, MC_ERRCAUSE(t0) | |
122 | sw zero, MC_ERRADDR(t0) | |
123 | ||
124 | /* Set clock ratio to 1:1 */ | |
125 | li t1, 0x03 /* clkrat=1:1, rddel=3 */ | |
126 | sw t1, MC_IOGP(t0) | |
127 | ||
128 | /* Clear Power-down registers */ | |
129 | sw zero, MC_SELFRFSH(t0) | |
130 | ||
131 | /* Set CAS Latency */ | |
132 | li t1, 0x00000020 /* CL = 2 */ | |
133 | sw t1, MC_MRSCODE(t0) | |
134 | ||
135 | /* Set word width to 16 bit */ | |
8bde7f77 | 136 | li t1, 0x2 |
c021880a WD |
137 | sw t1, MC_CFGDW(t0) |
138 | ||
139 | /* Set CS0 to SDRAM parameters */ | |
140 | li t1, 0x000014C9 | |
141 | sw t1, MC_CFGPB0(t0) | |
142 | ||
143 | /* Set SDRAM latency parameters */ | |
144 | li t1, 0x00026325 /* BC PC100 */ | |
145 | sw t1, MC_LATENCY(t0) | |
146 | ||
147 | /* Set SDRAM refresh rate */ | |
148 | li t1, 0x00000C30 /* 4K/64ms @ 100MHz */ | |
149 | sw t1, MC_TREFRESH(t0) | |
150 | ||
151 | /* Finally enable the controller */ | |
152 | li t1, 1 | |
153 | sw t1, MC_CTRLENA(t0) | |
154 | ||
155 | j ra | |
156 | nop |