[people/ms/u-boot.git] / board / inka4x0 / inka4x0.c

/*
 * (C) Copyright 2008-2009
 * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
 *
 * (C) Copyright 2009
 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * (C) Copyright 2004
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm/io.h>
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#if defined(CONFIG_DDR_MT46V16M16)
#include "mt46v16m16-75.h"
#elif defined(CONFIG_SDR_MT48LC16M16A2)
#include "mt48lc16m16a2-75.h"
#elif defined(CONFIG_DDR_MT46V32M16)
#include "mt46v32m16.h"
#elif defined(CONFIG_DDR_HYB25D512160BF)
#include "hyb25d512160bf.h"
#elif defined(CONFIG_DDR_K4H511638C)
#include "k4h511638c.h"
#else
#error "INKA4x0 SDRAM: invalid chip type specified!"
#endif

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	volatile struct mpc5xxx_sdram *sdram =
		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);

	/* precharge all banks */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);

#if SDRAM_DDR
	/* set mode register: extended mode */
	out_be32(&sdram->mode, SDRAM_EMODE);

	/* set mode register: reset DLL */
	out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
#endif

	/* precharge all banks */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);

	/* auto refresh */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);

	/* set mode register */
	out_be32(&sdram->mode, SDRAM_MODE);

	/* normal operation */
	out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *	      is something else than 0x00000000.
 */

phys_size_t initdram (int board_type)
{
	volatile struct mpc5xxx_mmap_ctl *mm =
		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	volatile struct mpc5xxx_cdm     *cdm =
		(struct mpc5xxx_cdm *)      MPC5XXX_CDM;
	volatile struct mpc5xxx_sdram *sdram =
		(struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
	ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
	long test1, test2;

	/* setup SDRAM chip selects */
	out_be32(&mm->sdram0, 0x0000001c);	/* 512MB at 0x0 */
	out_be32(&mm->sdram1, 0x40000000);	/* disabled */

	/* setup config registers */
	out_be32(&sdram->config1, SDRAM_CONFIG1);
	out_be32(&sdram->config2, SDRAM_CONFIG2);

#if SDRAM_DDR
	/* set tap delay */
	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		out_be32(&mm->sdram0, 0x13 +
			 __builtin_ffs(dramsize >> 20) - 1);
	} else {
		out_be32(&mm->sdram0, 0); /* disabled */
	}

	out_be32(&mm->sdram1, dramsize); /* disabled */
#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = in_be32(&mm->sdram0) & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}
#endif /* CONFIG_SYS_RAMBOOT */

	return dramsize;
}

int checkboard (void)
{
	puts ("Board: INKA 4X0\n");
	return 0;
}

void flash_preinit(void)
{
	volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;

	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT (CS0) cannot be cleared when
	 * executing in flash.
	 */
	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
}

int misc_init_f (void)
{
	volatile struct mpc5xxx_gpio	*gpio    =
		(struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
	volatile struct mpc5xxx_wu_gpio	*wu_gpio =
		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	volatile struct mpc5xxx_gpt	*gpt;
	char tmp[10];
	int i, br;

	i = getenv_r("brightness", tmp, sizeof(tmp));
	br = (i > 0)
		? (int) simple_strtoul (tmp, NULL, 10)
		: CONFIG_SYS_BRIGHTNESS;
	if (br > 255)
		br = 255;

	/* Initialize GPIO output pins.
	 */
	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
	for (i = 0; i <= 5; i++) {
		gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
		out_be32(&gpt->emsr, 0x34);
	}

	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
	gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
	out_be32(&gpt->emsr,  0);		/* Disable */
	out_be32(&gpt->cir,   0x020000fe);
	out_be32(&gpt->pwmcr, (br << 16));
	out_be32(&gpt->emsr,  0x3);		/* Enable PWM mode and start */

	/* Configure PSC3_6,7 as GPIO output */
	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
	setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
					  MPC5XXX_GPIO_SIMPLE_PSC3_7);

	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
				     MPC5XXX_GPIO_WKUP_7 |
				     MPC5XXX_GPIO_WKUP_PSC3_9);
	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
				     MPC5XXX_GPIO_WKUP_7 |
				     MPC5XXX_GPIO_WKUP_PSC3_9);

	/* Set LR mirror bit because it is low-active */
	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);

	/* Reset Coral-P graphics controller */
	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);

	/* Enable display backlight */
	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
	setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);

	/*
	 * Configure three wire serial interface to RTC (PSC1_4,
	 * PSC2_4, PSC3_4, PSC3_5)
	 */
	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
				     MPC5XXX_GPIO_WKUP_PSC2_4);
	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
				     MPC5XXX_GPIO_WKUP_PSC2_4);
	clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
				     MPC5XXX_GPIO_SINT_PSC3_5);
	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
				     MPC5XXX_GPIO_SINT_PSC3_5);
	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
	clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);

	return 0;
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif
Commit	Line	Data
138ff60c	1	/*
7b5611cd DZ	2	* (C) Copyright 2008-2009
	3	* Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
	4	*
	5	* (C) Copyright 2009
	6	* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
138ff60c WD	7	*
	8	* (C) Copyright 2004
	9	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	10	*
	11	* (C) Copyright 2004
	12	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	13	*
7b5611cd DZ	14	* (C) Copyright 2003-2004
	15	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	16	*
138ff60c WD	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35
e979e85f	36	#include <asm/io.h>
138ff60c WD	37	#include <common.h>
	38	#include <mpc5xxx.h>
	39	#include <pci.h>
	40
5fb6d719	41	#if defined(CONFIG_DDR_MT46V16M16)
138ff60c	42	#include "mt46v16m16-75.h"
5fb6d719	43	#elif defined(CONFIG_SDR_MT48LC16M16A2)
138ff60c	44	#include "mt48lc16m16a2-75.h"
5fb6d719 MB	45	#elif defined(CONFIG_DDR_MT46V32M16)
	46	#include "mt46v32m16.h"
	47	#elif defined(CONFIG_DDR_HYB25D512160BF)
	48	#include "hyb25d512160bf.h"
	49	#elif defined(CONFIG_DDR_K4H511638C)
	50	#include "k4h511638c.h"
	51	#else
	52	#error "INKA4x0 SDRAM: invalid chip type specified!"
138ff60c WD	53	#endif
138ff60c WD	54
6d0f6bcf	55	#ifndef CONFIG_SYS_RAMBOOT
138ff60c WD	56	static void sdram_start (int hi_addr)
138ff60c WD	57	{
2344bb8d DZ	58	volatile struct mpc5xxx_sdram *sdram =
2344bb8d DZ	59	(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
138ff60c WD	60	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	61
	62	/* unlock mode register */
2344bb8d	63	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit);
138ff60c WD	64
138ff60c WD	65	/* precharge all banks */
2344bb8d	66	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit);
138ff60c WD	67
	68	#if SDRAM_DDR
	69	/* set mode register: extended mode */
2344bb8d	70	out_be32(&sdram->mode, SDRAM_EMODE);
138ff60c WD	71
138ff60c WD	72	/* set mode register: reset DLL */
2344bb8d	73	out_be32(&sdram->mode, SDRAM_MODE \| 0x04000000);
138ff60c WD	74	#endif
	75
	76	/* precharge all banks */
2344bb8d	77	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit);
138ff60c WD	78
138ff60c WD	79	/* auto refresh */
2344bb8d	80	out_be32(&sdram->ctrl, SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit);
138ff60c WD	81
138ff60c WD	82	/* set mode register */
2344bb8d	83	out_be32(&sdram->mode, SDRAM_MODE);
138ff60c WD	84
138ff60c WD	85	/* normal operation */
2344bb8d	86	out_be32(&sdram->ctrl, SDRAM_CONTROL \| hi_addr_bit);
138ff60c WD	87	}
	88	#endif
	89
	90	/*
	91	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	92	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
138ff60c WD	93	* is something else than 0x00000000.
	94	*/
	95
9973e3c6	96	phys_size_t initdram (int board_type)
138ff60c	97	{
2344bb8d DZ	98	volatile struct mpc5xxx_mmap_ctl *mm =
	99	(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
	100	volatile struct mpc5xxx_cdm *cdm =
	101	(struct mpc5xxx_cdm *) MPC5XXX_CDM;
	102	volatile struct mpc5xxx_sdram *sdram =
	103	(struct mpc5xxx_sdram *) MPC5XXX_SDRAM;
138ff60c	104	ulong dramsize = 0;
6d0f6bcf	105	#ifndef CONFIG_SYS_RAMBOOT
f23cb34c	106	long test1, test2;
138ff60c WD	107
138ff60c WD	108	/* setup SDRAM chip selects */
2344bb8d DZ	109	out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */
2344bb8d DZ	110	out_be32(&mm->sdram1, 0x40000000); /* disabled */
138ff60c WD	111
138ff60c WD	112	/* setup config registers */
2344bb8d DZ	113	out_be32(&sdram->config1, SDRAM_CONFIG1);
2344bb8d DZ	114	out_be32(&sdram->config2, SDRAM_CONFIG2);
138ff60c WD	115
	116	#if SDRAM_DDR
	117	/* set tap delay */
2344bb8d	118	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
138ff60c WD	119	#endif
	120
	121	/* find RAM size using SDRAM CS0 only */
	122	sdram_start(0);
6d0f6bcf	123	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
138ff60c	124	sdram_start(1);
6d0f6bcf	125	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
138ff60c WD	126	if (test1 > test2) {
	127	sdram_start(0);
	128	dramsize = test1;
	129	} else {
	130	dramsize = test2;
	131	}
	132
	133	/* memory smaller than 1MB is impossible */
	134	if (dramsize < (1 << 20)) {
	135	dramsize = 0;
	136	}
	137
	138	/* set SDRAM CS0 size according to the amount of RAM found */
	139	if (dramsize > 0) {
2344bb8d DZ	140	out_be32(&mm->sdram0, 0x13 +
2344bb8d DZ	141	__builtin_ffs(dramsize >> 20) - 1);
138ff60c	142	} else {
2344bb8d	143	out_be32(&mm->sdram0, 0); /* disabled */
138ff60c WD	144	}
138ff60c WD	145
2344bb8d	146	out_be32(&mm->sdram1, dramsize); /* disabled */
6d0f6bcf	147	#else /* CONFIG_SYS_RAMBOOT */
138ff60c WD	148
138ff60c WD	149	/* retrieve size of memory connected to SDRAM CS0 */
2344bb8d	150	dramsize = in_be32(&mm->sdram0) & 0xFF;
138ff60c WD	151	if (dramsize >= 0x13) {
	152	dramsize = (1 << (dramsize - 0x13)) << 20;
	153	} else {
	154	dramsize = 0;
	155	}
6d0f6bcf	156	#endif /* CONFIG_SYS_RAMBOOT */
138ff60c	157
138ff60c WD	158	return dramsize;
	159	}
	160
	161	int checkboard (void)
	162	{
08f27278	163	puts ("Board: INKA 4X0\n");
138ff60c WD	164	return 0;
	165	}
	166
	167	void flash_preinit(void)
	168	{
2344bb8d DZ	169	volatile struct mpc5xxx_lpb lpb = (struct mpc5xxx_lpb )MPC5XXX_LPB;
2344bb8d DZ	170
138ff60c WD	171	/*
	172	* Now, when we are in RAM, enable flash write
	173	* access for detection process.
2344bb8d	174	* Note that CS_BOOT (CS0) cannot be cleared when
138ff60c WD	175	* executing in flash.
138ff60c WD	176	*/
2344bb8d	177	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
138ff60c	178	}
436be29c	179
151ab83a WD	180	int misc_init_f (void)
151ab83a WD	181	{
2344bb8d DZ	182	volatile struct mpc5xxx_gpio *gpio =
	183	(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
	184	volatile struct mpc5xxx_wu_gpio *wu_gpio =
	185	(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
	186	volatile struct mpc5xxx_gpt *gpt;
f23cb34c	187	char tmp[10];
a0bdf49e WD	188	int i, br;
	189
	190	i = getenv_r("brightness", tmp, sizeof(tmp));
	191	br = (i > 0)
	192	? (int) simple_strtoul (tmp, NULL, 10)
6d0f6bcf	193	: CONFIG_SYS_BRIGHTNESS;
a0bdf49e WD	194	if (br > 255)
	195	br = 255;
	196
f4733a07 WD	197	/* Initialize GPIO output pins.
f4733a07 WD	198	*/
342717f7	199	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
2344bb8d DZ	200	for (i = 0; i <= 5; i++) {
	201	gpt = (struct mpc5xxx_gpt )(MPC5XXX_GPT + (i 0x10));
	202	out_be32(&gpt->emsr, 0x34);
	203	}
f4733a07	204
a0bdf49e	205	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
2344bb8d DZ	206	gpt = (struct mpc5xxx_gpt )(MPC5XXX_GPT + (7 0x10));
	207	out_be32(&gpt->emsr, 0); /* Disable */
	208	out_be32(&gpt->cir, 0x020000fe);
	209	out_be32(&gpt->pwmcr, (br << 16));
	210	out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */
f4733a07 WD	211
f4733a07 WD	212	/* Configure PSC3_6,7 as GPIO output */
2344bb8d DZ	213	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 \|
	214	MPC5XXX_GPIO_SIMPLE_PSC3_7);
	215	setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 \|
	216	MPC5XXX_GPIO_SIMPLE_PSC3_7);
f4733a07 WD	217
f4733a07 WD	218	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
2344bb8d DZ	219	setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 \|
	220	MPC5XXX_GPIO_WKUP_7 \|
	221	MPC5XXX_GPIO_WKUP_PSC3_9);
	222	setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 \|
	223	MPC5XXX_GPIO_WKUP_7 \|
	224	MPC5XXX_GPIO_WKUP_PSC3_9);
f4733a07	225
342717f7	226	/* Set LR mirror bit because it is low-active */
2344bb8d DZ	227	setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7);
	228
	229	/* Reset Coral-P graphics controller */
	230	setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9);
	231
	232	/* Enable display backlight */
	233	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
	234	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
	235	setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8);
	236	setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8);
e979e85f DZ	237
	238	/*
	239	* Configure three wire serial interface to RTC (PSC1_4,
	240	* PSC2_4, PSC3_4, PSC3_5)
	241	*/
	242	setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 \|
	243	MPC5XXX_GPIO_WKUP_PSC2_4);
	244	setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 \|
	245	MPC5XXX_GPIO_WKUP_PSC2_4);
	246	clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
	247	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 \|
	248	MPC5XXX_GPIO_SINT_PSC3_5);
	249	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 \|
	250	MPC5XXX_GPIO_SINT_PSC3_5);
	251	setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
	252	clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
	253
f4733a07	254	return 0;
151ab83a WD	255	}
151ab83a WD	256
f4733a07	257	#ifdef CONFIG_PCI
436be29c WD	258	static struct pci_controller hose;
	259
	260	extern void pci_mpc5xxx_init(struct pci_controller *);
	261
	262	void pci_init_board(void)
	263	{
f4733a07	264	pci_mpc5xxx_init(&hose);
436be29c WD	265	}
436be29c WD	266	#endif