[people/ms/u-boot.git] / board / inka4x0 / inka4x0.c

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * (C) Copyright 2004
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m16a2-75.h"
#endif

#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 *	      is something else than 0x00000000.
 */

long int initdram (int board_type)
{
	ulong dramsize = 0;
#ifndef CFG_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
	sdram_start(1);
	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
			__builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
#else /* CFG_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CFG_RAMBOOT */

/*	return dramsize + dramsize2; */
	return dramsize;
}

int checkboard (void)
{
	puts ("Board: INKA 4X0\n");
	return 0;
}

void flash_preinit(void)
{
	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}

int misc_init_f (void)
{
	uchar tmp[10];
	int i, br;

	i = getenv_r("brightness", tmp, sizeof(tmp));
	br = (i > 0)
		? (int) simple_strtoul (tmp, NULL, 10)
		: CFG_BRIGHTNESS;
	if (br > 255)
		br = 255;

	/* Initialize GPIO output pins.
	 */
	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
	*(vu_long *)MPC5XXX_GPT0_ENABLE =
	*(vu_long *)MPC5XXX_GPT1_ENABLE =
	*(vu_long *)MPC5XXX_GPT2_ENABLE =
	*(vu_long *)MPC5XXX_GPT3_ENABLE =
	*(vu_long *)MPC5XXX_GPT4_ENABLE =
	*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;

	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
	*(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
	*(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */

	/* Configure PSC3_6,7 as GPIO output */
	*(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
	*(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;

	/* Configure PSC3_8 as GPIO output, no interrupt */
	*(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
	*(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
	*(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;

	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
	*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
	*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;

	/* Set LR mirror bit because it is low-active */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O    |= GPIO_WKUP_7;
	/*
	 * Reset Coral-P graphics controller
	 */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC3_9;
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC3_9;
	return 0;
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)

void init_ide_reset (void)
{
	debug ("init_ide_reset\n");

	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
	/* Deassert reset */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
}

void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
		/* Make a delay. MPC5200 spec says 25 usec min */
		udelay(500000);
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
	}
}
#endif
Commit	Line	Data
138ff60c WD	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
	8	* (C) Copyright 2004
	9	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#include <common.h>
	31	#include <mpc5xxx.h>
	32	#include <pci.h>
	33
	34	#if defined(CONFIG_MPC5200_DDR)
	35	#include "mt46v16m16-75.h"
	36	#else
	37	#include "mt48lc16m16a2-75.h"
	38	#endif
	39
	40	#ifndef CFG_RAMBOOT
	41	static void sdram_start (int hi_addr)
	42	{
	43	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	44
	45	/* unlock mode register */
f4733a07	46	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
138ff60c WD	47	__asm__ volatile ("sync");
	48
	49	/* precharge all banks */
f4733a07	50	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
138ff60c WD	51	__asm__ volatile ("sync");
	52
	53	#if SDRAM_DDR
	54	/* set mode register: extended mode */
	55	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	56	__asm__ volatile ("sync");
	57
	58	/* set mode register: reset DLL */
	59	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	60	__asm__ volatile ("sync");
	61	#endif
	62
	63	/* precharge all banks */
f4733a07	64	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
138ff60c WD	65	__asm__ volatile ("sync");
	66
	67	/* auto refresh */
f4733a07	68	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
138ff60c WD	69	__asm__ volatile ("sync");
	70
	71	/* set mode register */
	72	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	73	__asm__ volatile ("sync");
	74
	75	/* normal operation */
	76	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	77	__asm__ volatile ("sync");
	78	}
	79	#endif
	80
	81	/*
	82	* ATTENTION: Although partially referenced initdram does NOT make real use
	83	* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
	84	* is something else than 0x00000000.
	85	*/
	86
	87	long int initdram (int board_type)
	88	{
	89	ulong dramsize = 0;
	90	#ifndef CFG_RAMBOOT
	91	ulong test1, test2;
	92
	93	/* setup SDRAM chip selects */
	94	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
	95	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
	96	__asm__ volatile ("sync");
	97
	98	/* setup config registers */
	99	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	100	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	101	__asm__ volatile ("sync");
	102
	103	#if SDRAM_DDR
	104	/* set tap delay */
	105	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	106	__asm__ volatile ("sync");
	107	#endif
	108
	109	/* find RAM size using SDRAM CS0 only */
	110	sdram_start(0);
	111	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
	112	sdram_start(1);
	113	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
	114	if (test1 > test2) {
	115	sdram_start(0);
	116	dramsize = test1;
	117	} else {
	118	dramsize = test2;
	119	}
	120
	121	/* memory smaller than 1MB is impossible */
	122	if (dramsize < (1 << 20)) {
	123	dramsize = 0;
	124	}
	125
	126	/* set SDRAM CS0 size according to the amount of RAM found */
	127	if (dramsize > 0) {
	128	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 +
	129	__builtin_ffs(dramsize >> 20) - 1;
	130	} else {
	131	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	132	}
133
134	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
135	#else /* CFG_RAMBOOT */
136
137	/* retrieve size of memory connected to SDRAM CS0 */
138	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
139	if (dramsize >= 0x13) {
140	dramsize = (1 << (dramsize - 0x13)) << 20;
141	} else {
142	dramsize = 0;
143	}
144
145	/* retrieve size of memory connected to SDRAM CS1 */
146	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
147	if (dramsize2 >= 0x13) {
148	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
149	} else {
150	dramsize2 = 0;
151	}
152
153	#endif /* CFG_RAMBOOT */
154
155	/* return dramsize + dramsize2; */
156	return dramsize;
157	}
158
159	int checkboard (void)
160	{
08f27278	161	puts ("Board: INKA 4X0\n");
138ff60c WD	162	return 0;
	163	}
	164
	165	void flash_preinit(void)
	166	{
	167	/*
	168	* Now, when we are in RAM, enable flash write
	169	* access for detection process.
	170	* Note that CS_BOOT cannot be cleared when
	171	* executing in flash.
	172	*/
	173	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	174	}
436be29c	175
151ab83a WD	176	int misc_init_f (void)
151ab83a WD	177	{
a0bdf49e WD	178	uchar tmp[10];
	179	int i, br;
	180
	181	i = getenv_r("brightness", tmp, sizeof(tmp));
	182	br = (i > 0)
	183	? (int) simple_strtoul (tmp, NULL, 10)
	184	: CFG_BRIGHTNESS;
	185	if (br > 255)
	186	br = 255;
	187
f4733a07 WD	188	/* Initialize GPIO output pins.
f4733a07 WD	189	*/
342717f7	190	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
f4733a07 WD	191	(vu_long )MPC5XXX_GPT0_ENABLE =
	192	(vu_long )MPC5XXX_GPT1_ENABLE =
	193	(vu_long )MPC5XXX_GPT2_ENABLE =
	194	(vu_long )MPC5XXX_GPT3_ENABLE =
	195	(vu_long )MPC5XXX_GPT4_ENABLE =
342717f7	196	(vu_long )MPC5XXX_GPT5_ENABLE = 0x34;
f4733a07	197
a0bdf49e WD	198	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
	199	(vu_long )MPC5XXX_GPT7_ENABLE = 0;/* Disable */
	200	(vu_long )MPC5XXX_GPT7_COUNTER = 0x020000fe;
	201	(vu_long )MPC5XXX_GPT7_PWMCFG = (br << 16);
	202	(vu_long )MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
f4733a07 WD	203
	204	/* Configure PSC3_6,7 as GPIO output */
	205	(vu_long )MPC5XXX_GPIO_ENABLE \|= 0x00003000;
	206	(vu_long )MPC5XXX_GPIO_DIR \|= 0x00003000;
	207
	208	/* Configure PSC3_8 as GPIO output, no interrupt */
	209	(vu_long )MPC5XXX_GPIO_SI_ENABLE \|= 0x04000000;
	210	(vu_long )MPC5XXX_GPIO_SI_DIR \|= 0x04000000;
	211	(vu_long )MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
	212
	213	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
	214	(vu_long )MPC5XXX_WU_GPIO_ENABLE \|= 0xc4000000;
	215	(vu_long )MPC5XXX_WU_GPIO_DIR \|= 0xc4000000;
	216
342717f7	217	/* Set LR mirror bit because it is low-active */
dae80f3c	218	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_WKUP_7;
151ab83a WD	219	/*
	220	* Reset Coral-P graphics controller
	221	*/
f4733a07 WD	222	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC3_9;
f4733a07 WD	223	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC3_9;
dae80f3c	224	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC3_9;
f4733a07	225	return 0;
151ab83a WD	226	}
151ab83a WD	227
f4733a07	228	#ifdef CONFIG_PCI
436be29c WD	229	static struct pci_controller hose;
	230
	231	extern void pci_mpc5xxx_init(struct pci_controller *);
	232
	233	void pci_init_board(void)
	234	{
f4733a07	235	pci_mpc5xxx_init(&hose);
436be29c WD	236	}
436be29c WD	237	#endif
b05dcb58	238
77a31854	239	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
b05dcb58	240
b05dcb58 WD	241	void init_ide_reset (void)
	242	{
	243	debug ("init_ide_reset\n");
	244
f4733a07	245	/* Configure PSC1_4 as GPIO output for ATA reset */
b05dcb58 WD	246	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
	247	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
	248	/* Deassert reset */
dae80f3c	249	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
b05dcb58 WD	250	}
	251
	252	void ide_set_reset (int idereset)
	253	{
	254	debug ("ide_reset(%d)\n", idereset);
	255
	256	if (idereset) {
dae80f3c	257	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
b05dcb58 WD	258	/* Make a delay. MPC5200 spec says 25 usec min */
	259	udelay(500000);
	260	} else {
dae80f3c	261	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
b05dcb58 WD	262	}
b05dcb58 WD	263	}
77a31854	264	#endif