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1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
8 | * (C) Copyright 2004 | |
9 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <common.h> | |
31 | #include <mpc5xxx.h> | |
32 | #include <pci.h> | |
33 | ||
34 | #if defined(CONFIG_MPC5200_DDR) | |
35 | #include "mt46v16m16-75.h" | |
36 | #else | |
37 | #include "mt48lc16m16a2-75.h" | |
38 | #endif | |
39 | ||
40 | #ifndef CFG_RAMBOOT | |
41 | static void sdram_start (int hi_addr) | |
42 | { | |
43 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
44 | ||
45 | /* unlock mode register */ | |
46 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | | |
47 | hi_addr_bit; | |
48 | __asm__ volatile ("sync"); | |
49 | ||
50 | /* precharge all banks */ | |
51 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | | |
52 | hi_addr_bit; | |
53 | __asm__ volatile ("sync"); | |
54 | ||
55 | #if SDRAM_DDR | |
56 | /* set mode register: extended mode */ | |
57 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; | |
58 | __asm__ volatile ("sync"); | |
59 | ||
60 | /* set mode register: reset DLL */ | |
61 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; | |
62 | __asm__ volatile ("sync"); | |
63 | #endif | |
64 | ||
65 | /* precharge all banks */ | |
66 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | | |
67 | hi_addr_bit; | |
68 | __asm__ volatile ("sync"); | |
69 | ||
70 | /* auto refresh */ | |
71 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | | |
72 | hi_addr_bit; | |
73 | __asm__ volatile ("sync"); | |
74 | ||
75 | /* set mode register */ | |
76 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; | |
77 | __asm__ volatile ("sync"); | |
78 | ||
79 | /* normal operation */ | |
80 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; | |
81 | __asm__ volatile ("sync"); | |
82 | } | |
83 | #endif | |
84 | ||
85 | /* | |
86 | * ATTENTION: Although partially referenced initdram does NOT make real use | |
87 | * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE | |
88 | * is something else than 0x00000000. | |
89 | */ | |
90 | ||
91 | long int initdram (int board_type) | |
92 | { | |
93 | ulong dramsize = 0; | |
94 | #ifndef CFG_RAMBOOT | |
95 | ulong test1, test2; | |
96 | ||
97 | /* setup SDRAM chip selects */ | |
98 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ | |
99 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ | |
100 | __asm__ volatile ("sync"); | |
101 | ||
102 | /* setup config registers */ | |
103 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; | |
104 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; | |
105 | __asm__ volatile ("sync"); | |
106 | ||
107 | #if SDRAM_DDR | |
108 | /* set tap delay */ | |
109 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; | |
110 | __asm__ volatile ("sync"); | |
111 | #endif | |
112 | ||
113 | /* find RAM size using SDRAM CS0 only */ | |
114 | sdram_start(0); | |
115 | test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); | |
116 | sdram_start(1); | |
117 | test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); | |
118 | if (test1 > test2) { | |
119 | sdram_start(0); | |
120 | dramsize = test1; | |
121 | } else { | |
122 | dramsize = test2; | |
123 | } | |
124 | ||
125 | /* memory smaller than 1MB is impossible */ | |
126 | if (dramsize < (1 << 20)) { | |
127 | dramsize = 0; | |
128 | } | |
129 | ||
130 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
131 | if (dramsize > 0) { | |
132 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + | |
133 | __builtin_ffs(dramsize >> 20) - 1; | |
134 | } else { | |
135 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ | |
136 | } | |
137 | ||
138 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ | |
139 | #else /* CFG_RAMBOOT */ | |
140 | ||
141 | /* retrieve size of memory connected to SDRAM CS0 */ | |
142 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; | |
143 | if (dramsize >= 0x13) { | |
144 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
145 | } else { | |
146 | dramsize = 0; | |
147 | } | |
148 | ||
149 | /* retrieve size of memory connected to SDRAM CS1 */ | |
150 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; | |
151 | if (dramsize2 >= 0x13) { | |
152 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | |
153 | } else { | |
154 | dramsize2 = 0; | |
155 | } | |
156 | ||
157 | #endif /* CFG_RAMBOOT */ | |
158 | ||
159 | /* return dramsize + dramsize2; */ | |
160 | return dramsize; | |
161 | } | |
162 | ||
163 | int checkboard (void) | |
164 | { | |
165 | puts ("Board: INKA 4X0 (Indatec GmbH & Co. KG)\n"); | |
166 | return 0; | |
167 | } | |
168 | ||
169 | void flash_preinit(void) | |
170 | { | |
171 | /* | |
172 | * Now, when we are in RAM, enable flash write | |
173 | * access for detection process. | |
174 | * Note that CS_BOOT cannot be cleared when | |
175 | * executing in flash. | |
176 | */ | |
177 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ | |
178 | } |