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16f21704 WD |
1 | /* |
2 | * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de> | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <common.h> | |
24 | #include <ioports.h> | |
25 | #include <mpc8260.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/immap_8260.h> | |
28 | ||
29 | int hwc_flash_size (void); | |
30 | int hwc_local_sdram_size (void); | |
31 | int hwc_main_sdram_size (void); | |
32 | int hwc_serial_number (void); | |
33 | int hwc_mac_address (char *str); | |
34 | int hwc_manufact_date (char *str); | |
35 | int seeprom_read (int addr, uchar * data, int size); | |
36 | ||
37 | /* | |
38 | * I/O Port configuration table | |
39 | * | |
40 | * if conf is 1, then that port pin will be configured at boot time | |
41 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
42 | * | |
43 | * The port definitions are taken from the old firmware (see | |
44 | * also SYS/H/4539.H): | |
45 | * | |
46 | * ppar psor pdir podr pdat | |
47 | * PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0 | |
48 | * PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290 | |
49 | * PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d | |
50 | * PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9 | |
51 | */ | |
52 | const iop_conf_t iop_conf_tab[4][32] = { | |
53 | ||
54 | /* Port A configuration */ | |
55 | { /* conf ppar psor pdir podr pdat */ | |
56 | {0, 1, 0, 0, 0, 0}, /* PA31 FCC1_TXENB SLAVE */ | |
57 | {0, 1, 0, 1, 0, 0}, /* PA30 FCC1_TXCLAV SLAVE */ | |
58 | {0, 1, 0, 1, 0, 0}, /* PA29 FCC1_TXSOC */ | |
59 | {0, 1, 0, 0, 0, 0}, /* PA28 FCC1_RXENB SLAVE */ | |
60 | {0, 1, 0, 0, 0, 0}, /* PA27 FCC1_RXSOC */ | |
61 | {0, 1, 0, 1, 0, 0}, /* PA26 FCC1_RXCLAV SLAVE */ | |
62 | {0, 1, 0, 1, 0, 1}, /* PA25 FCC1_TXD0 */ | |
63 | {0, 1, 0, 1, 0, 1}, /* PA24 FCC1_TXD1 */ | |
64 | {0, 1, 0, 1, 0, 1}, /* PA23 FCC1_TXD2 */ | |
65 | {0, 1, 0, 1, 0, 1}, /* PA22 FCC1_TXD3 */ | |
66 | {0, 1, 0, 1, 0, 1}, /* PA21 FCC1_TXD4 */ | |
67 | {0, 1, 0, 1, 0, 1}, /* PA20 FCC1_TXD5 */ | |
68 | {0, 1, 0, 1, 0, 1}, /* PA19 FCC1_TXD6 */ | |
69 | {0, 1, 0, 1, 0, 1}, /* PA18 FCC1_TXD7 */ | |
70 | {0, 1, 0, 0, 0, 0}, /* PA17 FCC1_RXD7 */ | |
71 | {0, 1, 0, 0, 0, 0}, /* PA16 FCC1_RXD6 */ | |
72 | {0, 1, 0, 0, 0, 0}, /* PA15 FCC1_RXD5 */ | |
73 | {0, 1, 0, 0, 0, 0}, /* PA14 FCC1_RXD4 */ | |
74 | {0, 1, 0, 0, 0, 0}, /* PA13 FCC1_RXD3 */ | |
75 | {0, 1, 0, 0, 0, 0}, /* PA12 FCC1_RXD2 */ | |
76 | {0, 1, 0, 0, 0, 0}, /* PA11 FCC1_RXD1 */ | |
77 | {0, 1, 0, 0, 0, 0}, /* PA10 FCC1_RXD0 */ | |
78 | {0, 1, 1, 1, 0, 1}, /* PA9 TDMA1_L1TXD */ | |
79 | {0, 1, 1, 0, 0, 0}, /* PA8 TDMA1_L1RXD */ | |
80 | {0, 0, 0, 0, 0, 0}, /* PA7 CONFIG0 */ | |
81 | {0, 1, 1, 0, 0, 1}, /* PA6 TDMA1_L1RSYNC */ | |
82 | {0, 0, 0, 1, 0, 0}, /* PA5 FCC2:RxAddr[2] */ | |
83 | {0, 0, 0, 1, 0, 0}, /* PA4 FCC2:RxAddr[1] */ | |
84 | {0, 0, 0, 1, 0, 0}, /* PA3 FCC2:RxAddr[0] */ | |
85 | {0, 0, 0, 1, 0, 0}, /* PA2 FCC2:TxAddr[0] */ | |
86 | {0, 0, 0, 1, 0, 0}, /* PA1 FCC2:TxAddr[1] */ | |
87 | {0, 0, 0, 1, 0, 0} /* PA0 FCC2:TxAddr[2] */ | |
88 | }, | |
89 | /* Port B configuration */ | |
90 | { /* conf ppar psor pdir podr pdat */ | |
91 | {0, 0, 0, 1, 0, 0}, /* PB31 FCC2_RXSOC */ | |
92 | {0, 0, 0, 1, 0, 0}, /* PB30 FCC2_TXSOC */ | |
93 | {0, 0, 0, 1, 0, 0}, /* PB29 FCC2_RXCLAV */ | |
94 | {0, 0, 0, 0, 0, 0}, /* PB28 CONFIG2 */ | |
95 | {0, 1, 1, 0, 0, 1}, /* PB27 FCC2_TXD0 */ | |
96 | {0, 1, 1, 0, 0, 0}, /* PB26 FCC2_TXD1 */ | |
97 | {0, 0, 0, 1, 0, 0}, /* PB25 FCC2_TXD4 */ | |
98 | {0, 1, 1, 0, 0, 1}, /* PB24 FCC2_TXD5 */ | |
99 | {0, 0, 0, 1, 0, 0}, /* PB23 FCC2_TXD6 */ | |
100 | {0, 1, 0, 1, 0, 1}, /* PB22 FCC2_TXD7 */ | |
101 | {0, 1, 0, 0, 0, 0}, /* PB21 FCC2_RXD7 */ | |
102 | {0, 1, 0, 0, 0, 0}, /* PB20 FCC2_RXD6 */ | |
103 | {0, 1, 0, 0, 0, 0}, /* PB19 FCC2_RXD5 */ | |
104 | {0, 0, 0, 1, 0, 0}, /* PB18 FCC2_RXD4 */ | |
105 | {1, 1, 0, 0, 0, 0}, /* PB17 FCC3_RX_DV */ | |
106 | {1, 1, 0, 0, 0, 0}, /* PB16 FCC3_RX_ER */ | |
107 | {1, 1, 0, 1, 0, 0}, /* PB15 FCC3_TX_ER */ | |
108 | {1, 1, 0, 1, 0, 0}, /* PB14 FCC3_TX_EN */ | |
109 | {1, 1, 0, 0, 0, 0}, /* PB13 FCC3_COL */ | |
110 | {1, 1, 0, 0, 0, 0}, /* PB12 FCC3_CRS */ | |
111 | {1, 1, 0, 0, 0, 0}, /* PB11 FCC3_RXD3 */ | |
112 | {1, 1, 0, 0, 0, 0}, /* PB10 FCC3_RXD2 */ | |
113 | {1, 1, 0, 0, 0, 0}, /* PB9 FCC3_RXD1 */ | |
114 | {1, 1, 0, 0, 0, 0}, /* PB8 FCC3_RXD0 */ | |
115 | {1, 1, 0, 1, 0, 1}, /* PB7 FCC3_TXD0 */ | |
116 | {1, 1, 0, 1, 0, 1}, /* PB6 FCC3_TXD1 */ | |
117 | {1, 1, 0, 1, 0, 1}, /* PB5 FCC3_TXD2 */ | |
118 | {1, 1, 0, 1, 0, 1}, /* PB4 FCC3_TXD3 */ | |
119 | {0, 0, 0, 0, 0, 0}, /* PB3 */ | |
120 | {0, 0, 0, 0, 0, 0}, /* PB2 */ | |
121 | {0, 0, 0, 0, 0, 0}, /* PB1 */ | |
122 | {0, 0, 0, 0, 0, 0}, /* PB0 */ | |
123 | }, | |
124 | /* Port C configuration */ | |
125 | { /* conf ppar psor pdir podr pdat */ | |
126 | {0, 1, 0, 0, 0, 1}, /* PC31 CLK1 */ | |
127 | {0, 0, 0, 1, 0, 0}, /* PC30 U1MASTER_N */ | |
128 | {0, 1, 0, 0, 0, 1}, /* PC29 CLK3 */ | |
129 | {0, 0, 0, 1, 0, 1}, /* PC28 -MT90220_RST */ | |
130 | {0, 1, 0, 0, 0, 1}, /* PC27 CLK5 */ | |
131 | {0, 0, 0, 1, 0, 1}, /* PC26 -QUADFALC_RST */ | |
132 | {0, 1, 1, 1, 0, 1}, /* PC25 BRG4 */ | |
133 | {1, 0, 0, 1, 0, 0}, /* PC24 MDIO */ | |
134 | {1, 0, 0, 1, 0, 0}, /* PC23 MDC */ | |
135 | {0, 1, 0, 0, 0, 1}, /* PC22 CLK10 */ | |
136 | {0, 0, 0, 1, 0, 0}, /* PC21 */ | |
137 | {0, 1, 0, 0, 0, 1}, /* PC20 CLK12 */ | |
138 | {0, 1, 0, 0, 0, 1}, /* PC19 CLK13 */ | |
139 | {1, 1, 0, 0, 0, 1}, /* PC18 CLK14 */ | |
140 | {0, 1, 0, 0, 0, 0}, /* PC17 CLK15 */ | |
141 | {1, 1, 0, 0, 0, 1}, /* PC16 CLK16 */ | |
142 | {0, 1, 1, 0, 0, 0}, /* PC15 FCC1_TXADDR0 SLAVE */ | |
143 | {0, 1, 1, 0, 0, 0}, /* PC14 FCC1_RXADDR0 SLAVE */ | |
144 | {0, 1, 1, 0, 0, 0}, /* PC13 FCC1_TXADDR1 SLAVE */ | |
145 | {0, 1, 1, 0, 0, 0}, /* PC12 FCC1_RXADDR1 SLAVE */ | |
146 | {0, 0, 0, 1, 0, 0}, /* PC11 FCC2_RXD2 */ | |
147 | {0, 0, 0, 1, 0, 0}, /* PC10 FCC2_RXD3 */ | |
148 | {0, 0, 0, 1, 0, 1}, /* PC9 LTMODE */ | |
149 | {0, 0, 0, 1, 0, 1}, /* PC8 SELSYNC */ | |
150 | {0, 1, 1, 0, 0, 0}, /* PC7 FCC1_TXADDR2 SLAVE */ | |
151 | {0, 1, 1, 0, 0, 0}, /* PC6 FCC1_RXADDR2 SLAVE */ | |
152 | {0, 0, 0, 1, 0, 0}, /* PC5 FCC2_TXCLAV MASTER */ | |
153 | {0, 0, 0, 1, 0, 0}, /* PC4 FCC2_RXENB MASTER */ | |
154 | {0, 0, 0, 1, 0, 0}, /* PC3 FCC2_TXD2 */ | |
155 | {0, 0, 0, 1, 0, 0}, /* PC2 FCC2_TXD3 */ | |
156 | {0, 0, 0, 0, 0, 1}, /* PC1 PTMC -PTEENB */ | |
157 | {0, 0, 0, 1, 0, 1}, /* PC0 COMCLK_N */ | |
158 | }, | |
159 | /* Port D configuration */ | |
160 | { /* conf ppar psor pdir podr pdat */ | |
161 | {0, 0, 0, 1, 0, 1}, /* PD31 -CAM_RST */ | |
162 | {0, 0, 0, 1, 0, 0}, /* PD30 FCC2_TXENB */ | |
163 | {0, 1, 1, 0, 0, 0}, /* PD29 FCC1_RXADDR3 SLAVE */ | |
164 | {0, 1, 1, 0, 0, 1}, /* PD28 TDMC1_L1TXD */ | |
165 | {0, 1, 1, 0, 0, 0}, /* PD27 TDMC1_L1RXD */ | |
166 | {0, 1, 1, 0, 0, 1}, /* PD26 TDMC1_L1RSYNC */ | |
167 | {0, 0, 0, 1, 0, 1}, /* PD25 LED0 -OFF */ | |
168 | {0, 0, 0, 1, 0, 1}, /* PD24 LED5 -OFF */ | |
169 | {1, 0, 0, 1, 0, 1}, /* PD23 -LXT971_RST */ | |
170 | {0, 1, 1, 0, 0, 1}, /* PD22 TDMA2_L1TXD */ | |
171 | {0, 1, 1, 0, 0, 0}, /* PD21 TDMA2_L1RXD */ | |
172 | {0, 1, 1, 0, 0, 1}, /* PD20 TDMA2_L1RSYNC */ | |
173 | {0, 0, 0, 1, 0, 0}, /* PD19 FCC2_TXADDR3 */ | |
174 | {0, 0, 0, 1, 0, 0}, /* PD18 FCC2_RXADDR3 */ | |
175 | {0, 1, 0, 1, 0, 0}, /* PD17 BRG2 */ | |
176 | {0, 0, 0, 1, 0, 0}, /* PD16 */ | |
177 | {0, 0, 0, 1, 0, 0}, /* PD15 PT2TO1 */ | |
178 | {0, 0, 0, 1, 0, 1}, /* PD14 PT4TO3 */ | |
179 | {0, 0, 0, 1, 0, 1}, /* PD13 -SWMODE */ | |
180 | {0, 0, 0, 1, 0, 1}, /* PD12 -PTMODE */ | |
181 | {0, 0, 0, 1, 0, 0}, /* PD11 FCC2_RXD0 */ | |
182 | {0, 0, 0, 1, 0, 0}, /* PD10 FCC2_RXD1 */ | |
183 | {1, 1, 0, 1, 0, 1}, /* PD9 SMC1_SMTXD */ | |
184 | {1, 1, 0, 0, 0, 1}, /* PD8 SMC1_SMRXD */ | |
185 | {0, 1, 1, 0, 0, 0}, /* PD7 FCC1_TXADDR3 SLAVE */ | |
186 | {0, 0, 0, 1, 0, 0}, /* PD6 IMAMODE */ | |
187 | {0, 0, 0, 0, 0, 0}, /* PD5 CONFIG2 */ | |
188 | {0, 1, 0, 1, 0, 0}, /* PD4 BRG8 */ | |
189 | {0, 0, 0, 0, 0, 0}, /* PD3 */ | |
190 | {0, 0, 0, 0, 0, 0}, /* PD2 */ | |
191 | {0, 0, 0, 0, 0, 0}, /* PD1 */ | |
192 | {0, 0, 0, 0, 0, 0}, /* PD0 */ | |
193 | } | |
194 | }; | |
195 | ||
196 | long int initdram (int board_type) | |
197 | { | |
198 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
199 | volatile memctl8260_t *memctl = &immap->im_memctl; | |
200 | volatile uchar *base; | |
c83bf6a2 WD |
201 | ulong maxsize; |
202 | int i; | |
16f21704 WD |
203 | |
204 | memctl->memc_psrt = CFG_PSRT; | |
205 | memctl->memc_mptpr = CFG_MPTPR; | |
206 | ||
207 | #ifndef CFG_RAMBOOT | |
208 | immap->im_siu_conf.sc_ppc_acr = 0x00000026; | |
209 | immap->im_siu_conf.sc_ppc_alrh = 0x01276345; | |
210 | immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; | |
211 | immap->im_siu_conf.sc_lcl_acr = 0x00000000; | |
212 | immap->im_siu_conf.sc_lcl_alrh = 0x01234567; | |
213 | immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; | |
214 | immap->im_siu_conf.sc_tescr1 = 0x00004000; | |
215 | immap->im_siu_conf.sc_ltescr1 = 0x00004000; | |
216 | ||
217 | /* Init Main SDRAM */ | |
218 | #define OP_VALUE 0x404A241A | |
219 | #define OP_VALUE_M (OP_VALUE & 0x87FFFFFF); | |
220 | base = (uchar *) CFG_SDRAM_BASE; | |
221 | memctl->memc_psdmr = 0x28000000 | OP_VALUE_M; | |
222 | *base = 0xFF; | |
223 | memctl->memc_psdmr = 0x08000000 | OP_VALUE_M; | |
224 | for (i = 0; i < 8; i++) | |
225 | *base = 0xFF; | |
226 | memctl->memc_psdmr = 0x18000000 | OP_VALUE_M; | |
227 | *(base + 0x110) = 0xFF; | |
228 | memctl->memc_psdmr = OP_VALUE; | |
229 | memctl->memc_lsdmr = 0x4086A522; | |
230 | *base = 0xFF; | |
231 | ||
232 | /* We must be able to test a location outsize the maximum legal size | |
233 | * to find out THAT we are outside; but this address still has to be | |
234 | * mapped by the controller. That means, that the initial mapping has | |
235 | * to be (at least) twice as large as the maximum expected size. | |
236 | */ | |
237 | maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2; | |
238 | ||
c83bf6a2 | 239 | maxsize = get_ram_size((long *)base, maxsize); |
16f21704 | 240 | |
c83bf6a2 | 241 | memctl->memc_or1 |= ~(maxsize - 1); |
16f21704 | 242 | |
16f21704 WD |
243 | if (maxsize != hwc_main_sdram_size ()) |
244 | printf ("Oops: memory test has not found all memory!\n"); | |
245 | #endif | |
246 | ||
247 | icache_enable (); | |
248 | /* return total ram size of SDRAM */ | |
249 | return (maxsize); | |
250 | } | |
251 | ||
252 | int checkboard (void) | |
253 | { | |
254 | char string[32]; | |
255 | ||
256 | hwc_manufact_date (string); | |
257 | ||
258 | printf ("Board: Interphase 4539 (#%d %s)\n", | |
259 | hwc_serial_number (), | |
260 | string); | |
261 | ||
262 | #ifdef DEBUG | |
263 | printf ("Manufacturing date: %s\n", string); | |
264 | printf ("Serial number : %d\n", hwc_serial_number ()); | |
265 | printf ("FLASH size : %d MB\n", hwc_flash_size () >> 20); | |
266 | printf ("Main SDRAM size : %d MB\n", hwc_main_sdram_size () >> 20); | |
267 | printf ("Local SDRAM size : %d MB\n", hwc_local_sdram_size () >> 20); | |
268 | hwc_mac_address (string); | |
269 | printf ("MAC address : %s\n", string); | |
270 | #endif | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | int misc_init_r (void) | |
276 | { | |
277 | char *s, str[32]; | |
278 | int num; | |
279 | ||
280 | if ((s = getenv ("serial#")) == NULL && | |
281 | (num = hwc_serial_number ()) != -1) { | |
282 | sprintf (str, "%06d", num); | |
283 | setenv ("serial#", str); | |
284 | } | |
285 | if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) { | |
286 | setenv ("ethaddr", str); | |
287 | } | |
288 | return (0); | |
289 | } | |
290 | ||
291 | /*************************************************************** | |
292 | * We take some basic Hardware Configuration Parameter from the | |
293 | * Serial EEPROM conected to the PSpan bridge. We keep it as | |
294 | * simple as possible. | |
295 | */ | |
296 | int hwc_flash_size (void) | |
297 | { | |
298 | uchar byte; | |
299 | ||
300 | if (!seeprom_read (0x40, &byte, sizeof (byte))) { | |
301 | switch ((byte >> 2) & 0x3) { | |
302 | case 0x1: | |
303 | return 0x0400000; | |
304 | break; | |
305 | case 0x2: | |
306 | return 0x0800000; | |
307 | break; | |
308 | case 0x3: | |
309 | return 0x1000000; | |
310 | default: | |
311 | return 0x0100000; | |
312 | } | |
313 | } | |
314 | return -1; | |
315 | } | |
316 | int hwc_local_sdram_size (void) | |
317 | { | |
318 | uchar byte; | |
319 | ||
320 | if (!seeprom_read (0x40, &byte, sizeof (byte))) { | |
321 | switch ((byte & 0x03)) { | |
322 | case 0x1: | |
323 | return 0x0800000; | |
324 | case 0x2: | |
325 | return 0x1000000; | |
326 | default: | |
327 | return 0; /* not present */ | |
328 | } | |
329 | } | |
330 | return -1; | |
331 | } | |
332 | int hwc_main_sdram_size (void) | |
333 | { | |
334 | uchar byte; | |
335 | ||
336 | if (!seeprom_read (0x41, &byte, sizeof (byte))) { | |
337 | return 0x1000000 << ((byte >> 5) & 0x7); | |
338 | } | |
339 | return -1; | |
340 | } | |
341 | int hwc_serial_number (void) | |
342 | { | |
343 | int sn = -1; | |
344 | ||
77ddac94 | 345 | if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { |
16f21704 WD |
346 | sn = cpu_to_le32 (sn); |
347 | } | |
348 | return sn; | |
349 | } | |
350 | int hwc_mac_address (char *str) | |
351 | { | |
352 | char mac[6]; | |
353 | ||
77ddac94 | 354 | if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { |
16f21704 WD |
355 | sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n", |
356 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | |
357 | } else { | |
358 | strcpy (str, "ERROR"); | |
359 | return -1; | |
360 | } | |
361 | return 0; | |
362 | } | |
363 | int hwc_manufact_date (char *str) | |
364 | { | |
365 | uchar byte; | |
366 | int value; | |
367 | ||
368 | if (seeprom_read (0x92, &byte, sizeof (byte))) | |
369 | goto out; | |
370 | value = byte; | |
371 | if (seeprom_read (0x93, &byte, sizeof (byte))) | |
372 | goto out; | |
373 | value += byte << 8; | |
374 | sprintf (str, "%02d/%02d/%04d", | |
375 | value & 0x1F, (value >> 5) & 0xF, | |
376 | 1980 + ((value >> 9) & 0x1FF)); | |
377 | return 0; | |
378 | ||
379 | out: | |
380 | strcpy (str, "ERROR"); | |
381 | return -1; | |
382 | } | |
383 | ||
384 | #define PSPAN_ADDR 0xF0020000 | |
385 | #define EEPROM_REG 0x408 | |
386 | #define EEPROM_READ_CMD 0xA000 | |
387 | #define PSPAN_WRITE(a,v) \ | |
388 | *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() | |
389 | #define PSPAN_READ(a) \ | |
390 | *((volatile unsigned long *)(PSPAN_ADDR+(a))) | |
391 | ||
392 | int seeprom_read (int addr, uchar * data, int size) | |
393 | { | |
394 | ulong val, cmd; | |
395 | int i; | |
396 | ||
397 | for (i = 0; i < size; i++) { | |
398 | ||
399 | cmd = EEPROM_READ_CMD; | |
400 | cmd |= ((addr + i) << 24) & 0xff000000; | |
401 | ||
402 | /* Wait for ACT to authorize write */ | |
403 | while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) | |
404 | eieio (); | |
405 | ||
406 | /* Write command */ | |
407 | PSPAN_WRITE (EEPROM_REG, cmd); | |
408 | ||
409 | /* Wait for data to be valid */ | |
410 | while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) | |
411 | eieio (); | |
412 | /* Do it twice, first read might be erratic */ | |
413 | while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) | |
414 | eieio (); | |
415 | ||
416 | /* Read error */ | |
417 | if (val & 0x00000040) { | |
418 | return -1; | |
419 | } else { | |
420 | data[i] = (val >> 16) & 0xff; | |
421 | } | |
422 | } | |
423 | return 0; | |
424 | } |