[people/ms/u-boot.git] / board / isee / igep003x / board.c

/*
 * Board functions for IGEP COM AQUILA based boards
 *
 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

#ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr3_data = {
	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
};

static const struct cmd_control ddr3_cmd_ctrl_data = {
	.cmd0csratio = K4B2G1646EBIH9_RATIO,
	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,

	.cmd1csratio = K4B2G1646EBIH9_RATIO,
	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,

	.cmd2csratio = K4B2G1646EBIH9_RATIO,
	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
};

static struct emif_regs ddr3_emif_reg_data = {
	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
};

#define OSC    (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
		400, OSC-1, 1, -1, -1, -1, -1};

const struct dpll_params *get_dpll_ddr_params(void)
{
	return &dpll_ddr;
}

void set_uart_mux_conf(void)
{
	enable_uart0_pin_mux();
}

void set_mux_conf_regs(void)
{
	enable_board_pin_mux();
}

const struct ctrl_ioregs ioregs = {
	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
};

void sdram_init(void)
{
	config_ddr(400, &ioregs, &ddr3_data,
		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	gpmc_init();

	return 0;
}

#if defined(CONFIG_DRIVER_TI_CPSW)
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 0,
		.phy_if		= PHY_INTERFACE_MODE_RMII,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.bd_ram_ofs		= 0x2000,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};

int board_eth_init(bd_t *bis)
{
	int rv, ret = 0;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;

	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
		/* try reading mac address from efuse */
		mac_lo = readl(&cdev->macid0l);
		mac_hi = readl(&cdev->macid0h);
		mac_addr[0] = mac_hi & 0xFF;
		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
		mac_addr[4] = mac_lo & 0xFF;
		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
		if (is_valid_ethaddr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

	writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
	       &cdev->miisel);

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		ret += rv;

	return ret;
}
#endif
Commit	Line	Data
5f5c1d13	1	/*
3a2f0400	2	* Board functions for IGEP COM AQUILA based boards
5f5c1d13 EBS	3	*
	4	* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
5f5c1d13 EBS	7	*/
	8
	9	#include <common.h>
	10	#include <errno.h>
	11	#include <spl.h>
	12	#include <asm/arch/cpu.h>
	13	#include <asm/arch/hardware.h>
	14	#include <asm/arch/omap.h>
	15	#include <asm/arch/ddr_defs.h>
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/gpio.h>
	18	#include <asm/arch/mmc_host_def.h>
	19	#include <asm/arch/sys_proto.h>
	20	#include <asm/io.h>
	21	#include <asm/emif.h>
	22	#include <asm/gpio.h>
	23	#include <i2c.h>
	24	#include <miiphy.h>
	25	#include <cpsw.h>
	26	#include "board.h"
	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
5f5c1d13 EBS	30	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
5f5c1d13 EBS	31
5f5c1d13	32	#ifdef CONFIG_SPL_BUILD
5f5c1d13 EBS	33	static const struct ddr_data ddr3_data = {
	34	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
	35	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
	36	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
	37	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
5f5c1d13 EBS	38	};
	39
	40	static const struct cmd_control ddr3_cmd_ctrl_data = {
	41	.cmd0csratio = K4B2G1646EBIH9_RATIO,
5f5c1d13 EBS	42	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
	43
	44	.cmd1csratio = K4B2G1646EBIH9_RATIO,
5f5c1d13 EBS	45	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
	46
	47	.cmd2csratio = K4B2G1646EBIH9_RATIO,
5f5c1d13 EBS	48	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
	49	};
	50
	51	static struct emif_regs ddr3_emif_reg_data = {
	52	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
	53	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
	54	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
	55	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
	56	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
	57	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
	58	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
	59	};
94d77fb6 LV	60
	61	#define OSC (V_OSCK/1000000)
	62	const struct dpll_params dpll_ddr = {
94b32f60	63	400, OSC-1, 1, -1, -1, -1, -1};
94d77fb6 LV	64
	65	const struct dpll_params *get_dpll_ddr_params(void)
	66	{
	67	return &dpll_ddr;
	68	}
	69
0660481a	70	void set_uart_mux_conf(void)
5f5c1d13	71	{
5f5c1d13	72	enable_uart0_pin_mux();
0660481a	73	}
5f5c1d13	74
0660481a HS	75	void set_mux_conf_regs(void)
0660481a HS	76	{
5f5c1d13	77	enable_board_pin_mux();
0660481a	78	}
5f5c1d13	79
965de8b9 LV	80	const struct ctrl_ioregs ioregs = {
	81	.cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	82	.cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	83	.cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	84	.dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	85	.dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	86	};
	87
0660481a HS	88	void sdram_init(void)
0660481a HS	89	{
965de8b9	90	config_ddr(400, &ioregs, &ddr3_data,
5f5c1d13	91	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
5f5c1d13	92	}
0660481a	93	#endif
5f5c1d13 EBS	94
	95	/*
	96	* Basic board specific setup. Pinmux has been handled already.
	97	*/
	98	int board_init(void)
	99	{
73feefdc	100	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
5f5c1d13 EBS	101
	102	gpmc_init();
	103
	104	return 0;
	105	}
	106
	107	#if defined(CONFIG_DRIVER_TI_CPSW)
	108	static void cpsw_control(int enabled)
	109	{
	110	/* VTP can be added here */
	111
	112	return;
	113	}
	114
	115	static struct cpsw_slave_data cpsw_slaves[] = {
	116	{
	117	.slave_reg_ofs = 0x208,
	118	.sliver_reg_ofs = 0xd80,
9c653aad	119	.phy_addr = 0,
5f5c1d13 EBS	120	.phy_if = PHY_INTERFACE_MODE_RMII,
	121	},
	122	};
	123
	124	static struct cpsw_platform_data cpsw_data = {
	125	.mdio_base = CPSW_MDIO_BASE,
	126	.cpsw_base = CPSW_BASE,
	127	.mdio_div = 0xff,
	128	.channels = 8,
	129	.cpdma_reg_ofs = 0x800,
	130	.slaves = 1,
	131	.slave_data = cpsw_slaves,
	132	.ale_reg_ofs = 0xd00,
	133	.ale_entries = 1024,
	134	.host_port_reg_ofs = 0x108,
	135	.hw_stats_reg_ofs = 0x900,
6478cde6	136	.bd_ram_ofs = 0x2000,
5f5c1d13 EBS	137	.mac_control = (1 << 5),
	138	.control = cpsw_control,
	139	.host_port_num = 0,
	140	.version = CPSW_CTRL_VERSION_2,
	141	};
	142
	143	int board_eth_init(bd_t *bis)
	144	{
	145	int rv, ret = 0;
	146	uint8_t mac_addr[6];
	147	uint32_t mac_hi, mac_lo;
	148
	149	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
	150	/* try reading mac address from efuse */
	151	mac_lo = readl(&cdev->macid0l);
	152	mac_hi = readl(&cdev->macid0h);
	153	mac_addr[0] = mac_hi & 0xFF;
	154	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	155	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	156	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	157	mac_addr[4] = mac_lo & 0xFF;
	158	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
0adb5b76	159	if (is_valid_ethaddr(mac_addr))
5f5c1d13 EBS	160	eth_setenv_enetaddr("ethaddr", mac_addr);
	161	}
	162
dafd4db3 HS	163	writel((GMII1_SEL_RMII \| RMII1_IO_CLK_EN),
dafd4db3 HS	164	&cdev->miisel);
5f5c1d13 EBS	165
	166	rv = cpsw_register(&cpsw_data);
	167	if (rv < 0)
	168	printf("Error %d registering CPSW switch\n", rv);
	169	else
	170	ret += rv;
	171
	172	return ret;
	173	}
	174	#endif