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1 | /* |
2 | * Copyright (c) 2004 Picture Elements, Inc. | |
3 | * Stephen Williams (steve@icarus.com) | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
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6 | */ |
7 | ||
8 | #include <common.h> | |
b36df561 | 9 | #include <asm/ppc4xx.h> |
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10 | #include <asm/processor.h> |
11 | ||
12 | # define SDRAM_LEN 0x08000000 | |
13 | ||
14 | /* | |
15 | * this is even after checkboard. It returns the size of the SDRAM | |
16 | * that we have installed. This function is called by board_init_f | |
a47a12be | 17 | * in arch/powerpc/lib/board.c to initialize the memory and return what I |
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18 | * found. |
19 | */ | |
9973e3c6 | 20 | phys_size_t initdram (int board_type) |
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21 | { |
22 | /* Configure the SDRAMS */ | |
23 | ||
24 | /* disable memory controller */ | |
95b602ba | 25 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 26 | mtdcr (SDRAM0_CFGDATA, 0x00000000); |
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27 | |
28 | udelay (500); | |
29 | ||
30 | /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ | |
95b602ba | 31 | mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0); |
d1c3b275 | 32 | mtdcr (SDRAM0_CFGDATA, 0xffffffff); |
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33 | |
34 | /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ | |
95b602ba | 35 | mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1); |
d1c3b275 | 36 | mtdcr (SDRAM0_CFGDATA, 0xffffffff); |
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37 | |
38 | /* Clear SDRAM0_ECCCFG (disable ECC) */ | |
95b602ba | 39 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); |
d1c3b275 | 40 | mtdcr (SDRAM0_CFGDATA, 0x00000000); |
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41 | |
42 | /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ | |
95b602ba | 43 | mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR); |
d1c3b275 | 44 | mtdcr (SDRAM0_CFGDATA, 0xffffffff); |
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45 | |
46 | /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ | |
95b602ba | 47 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
d1c3b275 | 48 | mtdcr (SDRAM0_CFGDATA, 0x010a4016); |
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49 | |
50 | /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ | |
95b602ba | 51 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 52 | mtdcr (SDRAM0_CFGDATA, 0x00084001); |
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53 | |
54 | /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ | |
95b602ba | 55 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 56 | mtdcr (SDRAM0_CFGDATA, 0x04084001); |
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57 | |
58 | /* Memory Bank 2 Config == BE=0 */ | |
95b602ba | 59 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); |
d1c3b275 | 60 | mtdcr (SDRAM0_CFGDATA, 0x00000000); |
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61 | |
62 | /* Memory Bank 3 Config == BE=0 */ | |
95b602ba | 63 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); |
d1c3b275 | 64 | mtdcr (SDRAM0_CFGDATA, 0x00000000); |
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65 | |
66 | /* refresh timer = 0x400 */ | |
95b602ba | 67 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 68 | mtdcr (SDRAM0_CFGDATA, 0x04000000); |
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69 | |
70 | /* Power management idle timer set to the default. */ | |
95b602ba | 71 | mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT); |
d1c3b275 | 72 | mtdcr (SDRAM0_CFGDATA, 0x07c00000); |
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73 | |
74 | udelay (500); | |
75 | ||
76 | /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ | |
95b602ba | 77 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 78 | mtdcr (SDRAM0_CFGDATA, 0x80e00000); |
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79 | |
80 | return SDRAM_LEN; | |
81 | } | |
82 | ||
83 | /* | |
84 | * The U-Boot core, as part of the initialization to prepare for | |
85 | * loading the monitor into SDRAM, requests of this function that the | |
86 | * memory be tested. Return 0 if the memory tests OK. | |
87 | */ | |
88 | int testdram (void) | |
89 | { | |
90 | unsigned long idx; | |
91 | unsigned val; | |
92 | unsigned errors; | |
93 | volatile unsigned long *sdram; | |
94 | ||
95 | #ifdef DEBUG | |
96 | printf ("SDRAM Controller Registers --\n"); | |
97 | ||
95b602ba | 98 | mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); |
d1c3b275 | 99 | val = mfdcr (SDRAM0_CFGDATA); |
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100 | printf (" SDRAM0_CFG : 0x%08x\n", val); |
101 | ||
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102 | mtdcr (SDRAM0_CFGADDR, 0x24); |
103 | val = mfdcr (SDRAM0_CFGDATA); | |
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104 | printf (" SDRAM0_STATUS: 0x%08x\n", val); |
105 | ||
95b602ba | 106 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); |
d1c3b275 | 107 | val = mfdcr (SDRAM0_CFGDATA); |
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108 | printf (" SDRAM0_B0CR : 0x%08x\n", val); |
109 | ||
95b602ba | 110 | mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); |
d1c3b275 | 111 | val = mfdcr (SDRAM0_CFGDATA); |
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112 | printf (" SDRAM0_B1CR : 0x%08x\n", val); |
113 | ||
95b602ba | 114 | mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); |
d1c3b275 | 115 | val = mfdcr (SDRAM0_CFGDATA); |
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116 | printf (" SDRAM0_TR : 0x%08x\n", val); |
117 | ||
95b602ba | 118 | mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); |
d1c3b275 | 119 | val = mfdcr (SDRAM0_CFGDATA); |
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120 | printf (" SDRAM0_RTR : 0x%08x\n", val); |
121 | #endif | |
122 | ||
123 | /* Wait for memory to be ready by testing MRSCMPbit | |
124 | bit. Really, there should already have been plenty of time, | |
125 | given it was started long ago. But, best to check. */ | |
126 | for (idx = 0; idx < 1000000; idx += 1) { | |
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127 | mtdcr (SDRAM0_CFGADDR, 0x24); |
128 | val = mfdcr (SDRAM0_CFGDATA); | |
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129 | if (val & 0x80000000) |
130 | break; | |
131 | } | |
132 | ||
133 | if (!(val & 0x80000000)) { | |
134 | printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n"); | |
135 | return 1; | |
136 | } | |
137 | ||
138 | /* Start memory test. */ | |
139 | printf ("test: %u MB - ", SDRAM_LEN / 1048576); | |
140 | ||
6d0f6bcf | 141 | sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE; |
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142 | |
143 | printf ("write - "); | |
144 | for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { | |
145 | sdram[idx + 0] = idx; | |
146 | sdram[idx + 1] = ~idx; | |
147 | } | |
148 | ||
149 | printf ("read - "); | |
150 | errors = 0; | |
151 | for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { | |
152 | if (sdram[idx + 0] != idx) | |
153 | errors += 1; | |
154 | if (sdram[idx + 1] != ~idx) | |
155 | errors += 1; | |
156 | if (errors > 0) | |
157 | break; | |
158 | } | |
159 | ||
160 | if (errors > 0) { | |
161 | printf ("NOT OK\n"); | |
162 | printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n", | |
163 | sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx); | |
164 | return 1; | |
165 | } | |
166 | ||
167 | printf ("ok\n"); | |
168 | return 0; | |
169 | } |