[people/ms/u-boot.git] / board / jupiter / jupiter.c

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>
#include <libfdt.h>

#define SDRAM_DDR	0
#if 1
/* Settings Icecube */
#define SDRAM_MODE	0x00CD0000
#define SDRAM_CONTROL	0x504F0000
#define SDRAM_CONFIG1	0xD2322800
#define SDRAM_CONFIG2	0x8AD70000
#else
/*Settings Jupiter UB 1.0.0 */
#define SDRAM_MODE	0x008D0000
#define SDRAM_CONTROL	0xD04F0000
#define SDRAM_CONFIG1	0xf7277f00
#define SDRAM_CONFIG2	0x88b70004
#endif

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *            is something else than 0x00000000.
 */

phys_size_t initdram (int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
	uint svr, pvr;

#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else {
		dramsize2 = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20)) {
		dramsize2 = 0;
	}

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CONFIG_SYS_RAMBOOT */

	/*
	 * On MPC5200B we need to set the special configuration delay in the
	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	 *
	 * "The SDelay should be written to a value of 0x00000004. It is
	 * required to account for changes caused by normal wafer processing
	 * parameters."
	 */
	svr = get_svr();
	pvr = get_pvr();
	if ((SVR_MJREV(svr) >= 2) &&
	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {

		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
		__asm__ volatile ("sync");
	}

	return dramsize + dramsize2;
}

int checkboard (void)
{
	puts ("Board: Sauter (Jupiter)\n");
	return 0;
}

void flash_preinit(void)
{
	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}

int board_early_init_r (void)
{
	flash_preinit ();
	return 0;
}

void flash_afterinit(ulong size)
{
	if (size == 0x1000000) { /* adjust mapping */
		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
			START_REG(CONFIG_SYS_BOOTCS_START | size);
		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
	}
	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
}

int update_flash_size (int flash_size)
{
	flash_afterinit (flash_size);
	return 0;
}

int board_early_init_f (void)
{
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	return 0;
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)

void init_ide_reset (void)
{
	debug ("init_ide_reset\n");

	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
	/* Deassert reset */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
}

void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
		/* Make a delay. MPC5200 spec says 25 usec min */
		udelay(500000);
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
	}
}
#endif

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	return 0;
}
#endif
Commit	Line	Data
2605e90b HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
2605e90b HS	9	*/
	10
	11	#include <common.h>
	12	#include <mpc5xxx.h>
	13	#include <pci.h>
	14	#include <asm/processor.h>
cf2817a8	15	#include <libfdt.h>
2605e90b HS	16
	17	#define SDRAM_DDR 0
	18	#if 1
	19	/* Settings Icecube */
	20	#define SDRAM_MODE 0x00CD0000
	21	#define SDRAM_CONTROL 0x504F0000
	22	#define SDRAM_CONFIG1 0xD2322800
	23	#define SDRAM_CONFIG2 0x8AD70000
	24	#else
	25	/Settings Jupiter UB 1.0.0 /
	26	#define SDRAM_MODE 0x008D0000
	27	#define SDRAM_CONTROL 0xD04F0000
	28	#define SDRAM_CONFIG1 0xf7277f00
	29	#define SDRAM_CONFIG2 0x88b70004
	30	#endif
	31
6d0f6bcf	32	#ifndef CONFIG_SYS_RAMBOOT
2605e90b HS	33	static void sdram_start (int hi_addr)
	34	{
	35	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	36
	37	/* unlock mode register */
	38	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	39	__asm__ volatile ("sync");
	40
	41	/* precharge all banks */
	42	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	43	__asm__ volatile ("sync");
	44
	45	#if SDRAM_DDR
	46	/* set mode register: extended mode */
	47	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	48	__asm__ volatile ("sync");
	49
	50	/* set mode register: reset DLL */
	51	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	52	__asm__ volatile ("sync");
	53	#endif
	54
	55	/* precharge all banks */
	56	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	57	__asm__ volatile ("sync");
	58
	59	/* auto refresh */
	60	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	61	__asm__ volatile ("sync");
	62
	63	/* set mode register */
	64	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	65	__asm__ volatile ("sync");
	66
	67	/* normal operation */
	68	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	69	__asm__ volatile ("sync");
	70	}
	71	#endif
	72
	73	/*
	74	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	75	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
2605e90b HS	76	* is something else than 0x00000000.
	77	*/
	78
9973e3c6	79	phys_size_t initdram (int board_type)
2605e90b HS	80	{
	81	ulong dramsize = 0;
	82	ulong dramsize2 = 0;
	83	uint svr, pvr;
	84
6d0f6bcf	85	#ifndef CONFIG_SYS_RAMBOOT
2605e90b HS	86	ulong test1, test2;
	87
	88	/* setup SDRAM chip selects */
	89	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	90	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	91	__asm__ volatile ("sync");
	92
	93	/* setup config registers */
	94	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	95	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	96	__asm__ volatile ("sync");
	97
	98	#if SDRAM_DDR
	99	/* set tap delay */
	100	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	101	__asm__ volatile ("sync");
	102	#endif
	103
	104	/* find RAM size using SDRAM CS0 only */
	105	sdram_start(0);
6d0f6bcf	106	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
2605e90b	107	sdram_start(1);
6d0f6bcf	108	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
2605e90b HS	109	if (test1 > test2) {
	110	sdram_start(0);
	111	dramsize = test1;
	112	} else {
	113	dramsize = test2;
	114	}
	115
	116	/* memory smaller than 1MB is impossible */
	117	if (dramsize < (1 << 20)) {
	118	dramsize = 0;
	119	}
	120
	121	/* set SDRAM CS0 size according to the amount of RAM found */
	122	if (dramsize > 0) {
	123	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	124	} else {
	125	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	126	}
	127
	128	/* let SDRAM CS1 start right after CS0 */
	129	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
	130
	131	/* find RAM size using SDRAM CS1 only */
	132	if (!dramsize)
	133	sdram_start(0);
6d0f6bcf	134	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
2605e90b HS	135	if (!dramsize) {
2605e90b HS	136	sdram_start(1);
6d0f6bcf	137	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
2605e90b HS	138	}
	139	if (test1 > test2) {
	140	sdram_start(0);
	141	dramsize2 = test1;
	142	} else {
	143	dramsize2 = test2;
	144	}
	145
	146	/* memory smaller than 1MB is impossible */
	147	if (dramsize2 < (1 << 20)) {
	148	dramsize2 = 0;
	149	}
	150
	151	/* set SDRAM CS1 size according to the amount of RAM found */
	152	if (dramsize2 > 0) {
	153	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	154	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	155	} else {
	156	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	157	}
	158
6d0f6bcf	159	#else /* CONFIG_SYS_RAMBOOT */
2605e90b HS	160
	161	/* retrieve size of memory connected to SDRAM CS0 */
	162	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	163	if (dramsize >= 0x13) {
	164	dramsize = (1 << (dramsize - 0x13)) << 20;
	165	} else {
	166	dramsize = 0;
	167	}
	168
	169	/* retrieve size of memory connected to SDRAM CS1 */
	170	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	171	if (dramsize2 >= 0x13) {
	172	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	173	} else {
	174	dramsize2 = 0;
	175	}
	176
6d0f6bcf	177	#endif /* CONFIG_SYS_RAMBOOT */
2605e90b HS	178
	179	/*
	180	* On MPC5200B we need to set the special configuration delay in the
	181	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	182	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	183	*
	184	* "The SDelay should be written to a value of 0x00000004. It is
	185	* required to account for changes caused by normal wafer processing
	186	* parameters."
	187	*/
	188	svr = get_svr();
	189	pvr = get_pvr();
	190	if ((SVR_MJREV(svr) >= 2) &&
	191	(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
	192
	193	(vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;
	194	__asm__ volatile ("sync");
	195	}
	196
	197	return dramsize + dramsize2;
	198	}
	199
	200	int checkboard (void)
	201	{
	202	puts ("Board: Sauter (Jupiter)\n");
	203	return 0;
	204	}
	205
	206	void flash_preinit(void)
	207	{
	208	/*
	209	* Now, when we are in RAM, enable flash write
	210	* access for detection process.
	211	* Note that CS_BOOT cannot be cleared when
	212	* executing in flash.
	213	*/
2605e90b HS	214	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	215	}
	216
	217	int board_early_init_r (void)
	218	{
	219	flash_preinit ();
	220	return 0;
	221	}
	222
	223	void flash_afterinit(ulong size)
	224	{
	225	if (size == 0x1000000) { /* adjust mapping */
	226	(vu_long )MPC5XXX_BOOTCS_START = (vu_long )MPC5XXX_CS0_START =
6d0f6bcf	227	START_REG(CONFIG_SYS_BOOTCS_START \| size);
2605e90b	228	(vu_long )MPC5XXX_BOOTCS_STOP = (vu_long )MPC5XXX_CS0_STOP =
6d0f6bcf	229	STOP_REG(CONFIG_SYS_BOOTCS_START \| size, size);
2605e90b	230	}
2605e90b HS	231	(vu_long )MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
2605e90b HS	232	(vu_long )MPC5XXX_ADDECR \|= (1 << 16); /* enable CS0 */
2605e90b HS	233	}
	234
	235	int update_flash_size (int flash_size)
	236	{
	237	flash_afterinit (flash_size);
	238	return 0;
	239	}
	240
	241	int board_early_init_f (void)
	242	{
	243	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	244	return 0;
	245	}
	246
	247	#ifdef CONFIG_PCI
	248	static struct pci_controller hose;
	249
	250	extern void pci_mpc5xxx_init(struct pci_controller *);
	251
	252	void pci_init_board(void)
	253	{
	254	pci_mpc5xxx_init(&hose);
	255	}
	256	#endif
	257
d39b5741	258	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
2605e90b HS	259
	260	void init_ide_reset (void)
	261	{
	262	debug ("init_ide_reset\n");
	263
	264	/* Configure PSC1_4 as GPIO output for ATA reset */
	265	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
	266	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
	267	/* Deassert reset */
	268	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
	269	}
	270
	271	void ide_set_reset (int idereset)
	272	{
	273	debug ("ide_reset(%d)\n", idereset);
	274
	275	if (idereset) {
	276	(vu_long ) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
	277	/* Make a delay. MPC5200 spec says 25 usec min */
	278	udelay(500000);
	279	} else {
	280	(vu_long ) MPC5XXX_WU_GPIO_DATA_O \|= GPIO_PSC1_4;
	281	}
	282	}
d39b5741	283	#endif
2605e90b	284
cf2817a8	285	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	286	int ft_board_setup(void blob, bd_t bd)
2605e90b HS	287	{
2605e90b HS	288	ft_cpu_setup(blob, bd);
e895a4b0 SG	289
e895a4b0 SG	290	return 0;
2605e90b HS	291	}
2605e90b HS	292	#endif