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0ec005fe MV |
1 | # |
2 | # (C) Copyright 2009 | |
3 | # Marvell Semiconductor <www.marvell.com> | |
4 | # Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
5 | # | |
6 | # adopted to TK71 by | |
7 | # Nils Faerber <nils.faerber@kernelconcepts.de> | |
8 | # | |
1a459660 | 9 | # SPDX-License-Identifier: GPL-2.0+ |
0ec005fe | 10 | # |
b1e6c4c3 | 11 | # Refer doc/README.kwbimage for more details about how-to configure |
0ec005fe MV |
12 | # and create kirkwood boot image |
13 | # | |
14 | ||
15 | # Boot Media configurations | |
16 | BOOT_FROM nand | |
17 | NAND_ECC_MODE default | |
18 | NAND_PAGE_SIZE 0x0800 | |
19 | ||
20 | # SOC registers configuration using bootrom header extension | |
21 | # Maximum KWBIMAGE_MAX_CONFIG configurations allowed | |
22 | ||
23 | # Configure RGMII-0 interface pad voltage to 1.8V | |
24 | DATA 0xFFD100e0 0x1b1b1b9b | |
25 | ||
26 | #Dram initalization for SINGLE x16 CL=5 @ 400MHz | |
27 | DATA 0xFFD01400 0x43000c30 # DDR Configuration register | |
28 | # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) | |
29 | # bit23-14: zero | |
30 | # bit24: 1= enable exit self refresh mode on DDR access | |
31 | # bit25: 1 required | |
32 | # bit29-26: zero | |
33 | # bit31-30: 01 | |
34 | ||
35 | DATA 0xFFD01404 0x36543000 # DDR Controller Control Low | |
36 | # bit 4: 0=addr/cmd in smame cycle | |
37 | # bit 5: 0=clk is driven during self refresh, we don't care for APX | |
38 | # bit 6: 0=use recommended falling edge of clk for addr/cmd | |
39 | # bit14: 0=input buffer always powered up | |
40 | # bit18: 1=cpu lock transaction enabled | |
41 | # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 | |
42 | # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM | |
43 | # bit30-28: 3 required | |
44 | # bit31: 0=no additional STARTBURST delay | |
45 | ||
46 | DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) | |
47 | # bit3-0: TRAS lsbs | |
48 | # bit7-4: TRCD | |
49 | # bit11- 8: TRP | |
50 | # bit15-12: TWR | |
51 | # bit19-16: TWTR | |
52 | # bit20: TRAS msb | |
53 | # bit23-21: 0x0 | |
54 | # bit27-24: TRRD | |
55 | # bit31-28: TRTP | |
56 | ||
57 | DATA 0xFFD0140C 0x00000034 # DDR Timing (High) | |
58 | # bit6-0: TRFC | |
59 | # bit8-7: TR2R | |
60 | # bit10-9: TR2W | |
61 | # bit12-11: TW2W | |
62 | # bit31-13: zero required | |
63 | ||
64 | DATA 0xFFD01410 0x00000000 # DDR Address Control | |
65 | # bit1-0: 01, Cs0width=x16 | |
66 | # bit3-2: 10, Cs0size=512Mb | |
67 | # bit5-4: 01, Cs1width=x16 | |
68 | # bit7-6: 10, Cs1size=512Mb | |
69 | # bit9-8: 00, Cs2width=nonexistent | |
70 | # bit11-10: 00, Cs2size =nonexistent | |
71 | # bit13-12: 00, Cs3width=nonexistent | |
72 | # bit15-14: 00, Cs3size =nonexistent | |
73 | # bit16: 0, Cs0AddrSel | |
74 | # bit17: 0, Cs1AddrSel | |
75 | # bit18: 0, Cs2AddrSel | |
76 | # bit19: 0, Cs3AddrSel | |
77 | # bit31-20: 0 required | |
78 | ||
79 | DATA 0xFFD01414 0x00000000 # DDR Open Pages Control | |
80 | # bit0: 0, OpenPage enabled | |
81 | # bit31-1: 0 required | |
82 | ||
83 | DATA 0xFFD01418 0x00000000 # DDR Operation | |
84 | # bit3-0: 0x0, DDR cmd | |
85 | # bit31-4: 0 required | |
86 | ||
87 | DATA 0xFFD0141C 0x00000652 # DDR Mode | |
88 | # bit2-0: 2, BurstLen=2 required | |
89 | # bit3: 0, BurstType=0 required | |
90 | # bit6-4: 4, CL=5 | |
91 | # bit7: 0, TestMode=0 normal | |
92 | # bit8: 0, DLL reset=0 normal | |
93 | # bit11-9: 6, auto-precharge write recovery ???????????? | |
94 | # bit12: 0, PD must be zero | |
95 | # bit31-13: 0 required | |
96 | ||
97 | DATA 0xFFD01420 0x00000042 # DDR Extended Mode | |
98 | # bit0: 0, DDR DLL enabled | |
99 | # bit1: 0, DDR drive strenght normal | |
100 | # bit2: 0, DDR ODT control lsd (disabled) | |
101 | # bit5-3: 000, required | |
102 | # bit6: 1, DDR ODT control msb, (disabled) | |
103 | # bit9-7: 000, required | |
104 | # bit10: 0, differential DQS enabled | |
105 | # bit11: 0, required | |
106 | # bit12: 0, DDR output buffer enabled | |
107 | # bit31-13: 0 required | |
108 | ||
109 | DATA 0xFFD01424 0x0000F17F # DDR Controller Control High | |
110 | # bit2-0: 111, required | |
111 | # bit3 : 1 , MBUS Burst Chop disabled | |
112 | # bit6-4: 111, required | |
113 | # bit7 : 0 | |
114 | # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz | |
115 | # bit9 : 0 , no half clock cycle addition to dataout | |
116 | # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals | |
117 | # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh | |
118 | # bit15-12: 1111 required | |
119 | # bit31-16: 0 required | |
120 | ||
121 | DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) | |
122 | DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) | |
123 | ||
124 | DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 | |
125 | DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size | |
126 | # bit0: 1, Window enabled | |
127 | # bit1: 0, Write Protect disabled | |
128 | # bit3-2: 00, CS0 hit selected | |
129 | # bit23-4: ones, required | |
130 | # bit31-24: 0x0F, Size (i.e. 256MB) | |
131 | ||
132 | DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb | |
133 | DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1 | |
134 | ||
135 | DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled | |
136 | DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled | |
137 | ||
138 | DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low) | |
139 | # bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 | |
140 | # bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 | |
141 | # bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. | |
142 | # bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. | |
143 | DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) | |
144 | # bit1-0: 00, ODT0 controlled by ODT Control (low) register above | |
145 | # bit3-2: 01, ODT1 active NEVER! | |
146 | # bit31-4: zero, required | |
147 | ||
148 | DATA 0xFFD0149C 0x0000F80F # CPU ODT Control | |
149 | # bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 | |
150 | # bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm | |
151 | # bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm | |
152 | # bit14: 1, M_STARTBURST_IN ODT: Enabled | |
153 | # bit15: 1, DDR IO ODT Unit: Use ODT block | |
154 | DATA 0xFFD01480 0x00000001 # DDR Initialization Control | |
155 | #bit0=1, enable DDR init upon this register write | |
156 | ||
157 | # End of Header extension | |
158 | DATA 0x0 0x0 |