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misc: pmic: drop old Freescale's pmic driver
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1/*
2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
4 *
5 * Based on imx27lite.c:
6 * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
7 * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
8 * And:
9 * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 *
26 */
27#include <common.h>
28#include <asm/io.h>
29#include <asm/arch/imx-regs.h>
30#include <asm/arch/imx25-pinmux.h>
c2205f4d 31#include <asm/gpio.h>
e6d9b978 32#include <asm/arch/sys_proto.h>
6895d451 33
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34DECLARE_GLOBAL_DATA_PTR;
35
36#ifdef CONFIG_FEC_MXC
37void tx25_fec_init(void)
38{
39 struct iomuxc_mux_ctl *muxctl;
40 struct iomuxc_pad_ctl *padctl;
41 u32 val;
42 u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
43 struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE;
44 struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE;
45 u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
46
47 debug("tx25_fec_init\n");
48 /*
49 * fec pin init is generic
50 */
51 mx25_fec_init_pins();
52
53 /*
54 * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
55 *
56 * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
57 * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
58 */
59 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
60 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
61
62 writel(gpio_mux_mode, &muxctl->pad_d13);
63 writel(gpio_mux_mode, &muxctl->pad_d11);
64
65 writel(0x0, &padctl->pad_d13);
66 writel(0x0, &padctl->pad_d11);
67
68 /* drop PHY power and assert reset (low) */
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69 val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9));
70 writel(val, &gpio4->gpio_dr);
71 val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9);
72 writel(val, &gpio4->gpio_dir);
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73
74 mdelay(5);
75
76 debug("resetting phy\n");
77
78 /* turn on PHY power leaving reset asserted */
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79 val = readl(&gpio4->gpio_dr) | 1 << 9;
80 writel(val, &gpio4->gpio_dr);
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81
82 mdelay(10);
83
84 /*
85 * Setup some strapping pins that are latched by the PHY
86 * as reset goes high.
87 *
88 * Set PHY mode to 111
89 * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
90 * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
91 * mode2 is tied high so nothing to do
92 *
93 * Turn on RMII mode
94 * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
95 */
96 /*
97 * save three current mux modes and set each to gpio mode
98 */
99 saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0);
100 saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1);
101 saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv);
102
103 writel(gpio_mux_mode, &muxctl->pad_fec_rdata0);
104 writel(gpio_mux_mode, &muxctl->pad_fec_rdata1);
105 writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv);
106
107 /*
108 * set each to 1 and make each an output
109 */
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110 val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12);
111 writel(val, &gpio3->gpio_dr);
112 val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12);
113 writel(val, &gpio3->gpio_dir);
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114
115 mdelay(22); /* this value came from RedBoot */
116
117 /*
118 * deassert PHY reset
119 */
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120 val = readl(&gpio4->gpio_dr) | 1 << 7;
121 writel(val, &gpio4->gpio_dr);
122 writel(val, &gpio4->gpio_dr);
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123
124 mdelay(5);
125
126 /*
127 * set FEC pins back
128 */
129 writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0);
130 writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1);
131 writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv);
132}
133#else
134#define tx25_fec_init()
135#endif
136
137int board_init()
138{
139#ifdef CONFIG_MXC_UART
9aa720b1 140 mx25_uart1_init_pins();
6895d451 141#endif
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142 /* board id for linux */
143 gd->bd->bi_arch_number = MACH_TYPE_TX25;
144 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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145 return 0;
146}
147
148int board_late_init(void)
149{
150 tx25_fec_init();
151 return 0;
152}
153
154int dram_init (void)
155{
ab86f72c 156 /* dram_init must store complete ramsize in gd->ram_size */
a55d23cc 157 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
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158 PHYS_SDRAM_1_SIZE);
159 return 0;
160}
6895d451 161
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162void dram_init_banksize(void)
163{
6895d451 164 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
a55d23cc 165 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
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166 PHYS_SDRAM_1_SIZE);
167#if CONFIG_NR_DRAM_BANKS > 1
168 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
a55d23cc 169 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
6895d451 170 PHYS_SDRAM_2_SIZE);
ab86f72c 171#else
6895d451 172
ab86f72c 173#endif
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174}
175
176int checkboard(void)
177{
178 printf("KARO TX25\n");
179 return 0;
180}