[thirdparty/u-boot.git] / board / keymile / km_arm / km_arm.c

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Prafulla Wadaskar <prafulla@marvell.com>
 *
 * (C) Copyright 2009
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2010
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

#include <common.h>
#include <i2c.h>
#include <nand.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/arch/kirkwood.h>
#include <asm/arch/mpp.h>

#include "../common/common.h"

DECLARE_GLOBAL_DATA_PTR;

static int	io_dev;
extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);

/* Multi-Purpose Pins Functionality configuration */
u32 kwmpp_config[] = {
	MPP0_NF_IO2,
	MPP1_NF_IO3,
	MPP2_NF_IO4,
	MPP3_NF_IO5,
	MPP4_NF_IO6,
	MPP5_NF_IO7,
	MPP6_SYSRST_OUTn,
	MPP7_PEX_RST_OUTn,
#if defined(CONFIG_SOFT_I2C)
	MPP8_GPIO,		/* SDA */
	MPP9_GPIO,		/* SCL */
#endif
#if defined(CONFIG_HARD_I2C)
	MPP8_TW_SDA,
	MPP9_TW_SCK,
#endif
	MPP10_UART0_TXD,
	MPP11_UART0_RXD,
	MPP12_GPO,		/* Reserved */
	MPP13_UART1_TXD,
	MPP14_UART1_RXD,
	MPP15_GPIO,		/* Not used */
	MPP16_GPIO,		/* Not used */
	MPP17_GPIO,		/* Reserved */
	MPP18_NF_IO0,
	MPP19_NF_IO1,
	MPP20_GPIO,
	MPP21_GPIO,
	MPP22_GPIO,
	MPP23_GPIO,
	MPP24_GPIO,
	MPP25_GPIO,
	MPP26_GPIO,
	MPP27_GPIO,
	MPP28_GPIO,
	MPP29_GPIO,
	MPP30_GPIO,
	MPP31_GPIO,
	MPP32_GPIO,
	MPP33_GPIO,
	MPP34_GPIO,		/* CDL1 (input) */
	MPP35_GPIO,		/* CDL2 (input) */
	MPP36_GPIO,		/* MAIN_IRQ (input) */
	MPP37_GPIO,		/* BOARD_LED */
	MPP38_GPIO,		/* Piggy3 LED[1] */
	MPP39_GPIO,		/* Piggy3 LED[2] */
	MPP40_GPIO,		/* Piggy3 LED[3] */
	MPP41_GPIO,		/* Piggy3 LED[4] */
	MPP42_GPIO,		/* Piggy3 LED[5] */
	MPP43_GPIO,		/* Piggy3 LED[6] */
	MPP44_GPIO,		/* Piggy3 LED[7] */
	MPP45_GPIO,		/* Piggy3 LED[8] */
	MPP46_GPIO,		/* Reserved */
	MPP47_GPIO,		/* Reserved */
	MPP48_GPIO,		/* Reserved */
	MPP49_GPIO,		/* SW_INTOUTn */
	0
};

int ethernet_present(void)
{
	uchar	buf;
	int	ret = 0;

	if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
		printf ("%s: Error reading Boco\n", __FUNCTION__);
		return -1;
	}
	if ((buf & 0x40) == 0x40) {
		ret = 1;
	}
	return ret;
}

int misc_init_r(void)
{
	I2C_MUX_DEVICE	*i2cdev;
	char *str;
	int mach_type;

	/* add I2C Bus for I/O Expander */
	i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
	io_dev = i2cdev->busid;
	puts("Piggy:");
	if (ethernet_present() == 0)
		puts (" not");
	puts(" present\n");

	str = getenv("mach_type");
	if (str != NULL) {
		mach_type = simple_strtoul(str, NULL, 10);
		printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
		gd->bd->bi_arch_number = mach_type;
	}
	return 0;
}

int board_init(void)
{
	u32 tmp;

	kirkwood_mpp_conf(kwmpp_config);

	/*
	 * The FLASH_GPIO_PIN switches between using a
	 * NAND or a SPI FLASH. Set this pin on start
	 * to NAND mode.
	 */
	tmp = readl(KW_GPIO0_BASE);
	writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
	tmp = readl(KW_GPIO0_BASE + 4);
	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
	printf("KM: setting NAND mode\n");

	/*
	 * arch number of board
	 */
	gd->bd->bi_arch_number = MACH_TYPE_SUEN3;

	/* address of boot parameters */
	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;

#if defined(CONFIG_SOFT_I2C)
	/* init the GPIO for I2C Bitbang driver */
	kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
	kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
	kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
	kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
#endif
#if defined(CONFIG_SYS_EEPROM_WREN)
	kw_gpio_set_valid(SUEN3_ENV_WP, 38);
	kw_gpio_direction_output(SUEN3_ENV_WP, 1);
#endif
	return 0;
}

#if defined(CONFIG_CMD_SF)
int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	u32 tmp;
	if (argc < 2)
		return cmd_usage(cmdtp);

	if ((strcmp(argv[1], "off") == 0)) {
		printf("SPI FLASH disabled, NAND enabled\n");
		/* Multi-Purpose Pins Functionality configuration */
		kwmpp_config[0] = MPP0_NF_IO2;
		kwmpp_config[1] = MPP1_NF_IO3;
		kwmpp_config[2] = MPP2_NF_IO4;
		kwmpp_config[3] = MPP3_NF_IO5;

		kirkwood_mpp_conf(kwmpp_config);
		tmp = readl(KW_GPIO0_BASE);
		writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
	} else if ((strcmp(argv[1], "on") == 0)) {
		printf("SPI FLASH enabled, NAND disabled\n");
		/* Multi-Purpose Pins Functionality configuration */
		kwmpp_config[0] = MPP0_SPI_SCn;
		kwmpp_config[1] = MPP1_SPI_MOSI;
		kwmpp_config[2] = MPP2_SPI_SCK;
		kwmpp_config[3] = MPP3_SPI_MISO;

		kirkwood_mpp_conf(kwmpp_config);
		tmp = readl(KW_GPIO0_BASE);
		writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
	} else {
		return cmd_usage(cmdtp);
	}

	return 0;
}

U_BOOT_CMD(
	spitoggle,	2,	0,	do_spi_toggle,
	"En-/disable SPI FLASH access",
	"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
	);
#endif

#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
int dram_init(void)
{
	int i;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
						       kw_sdram_bs(i));
	}

	return 0;
}
#else
int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	/* Fix this */
	gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
				kw_sdram_bs(0));
	return 0;
}

void dram_init_banksize(void)
{
	int i;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
		gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
						       kw_sdram_bs(i));
	}
}
#endif

/* Configure and enable MV88E1118 PHY */
void reset_phy(void)
{
	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* reset the phy */
	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}

#if defined(CONFIG_HUSH_INIT_VAR)
int hush_init_var (void)
{
	ivm_read_eeprom ();
	return 0;
}
#endif

#if defined(CONFIG_BOOTCOUNT_LIMIT)
void bootcount_store (ulong a)
{
	volatile ulong *save_addr;
	volatile ulong size = 0;
	int i;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		size += gd->bd->bi_dram[i].size;
	}
	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
	writel(a, save_addr);
	writel(BOOTCOUNT_MAGIC, &save_addr[1]);
}

ulong bootcount_load (void)
{
	volatile ulong *save_addr;
	volatile ulong size = 0;
	int i;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		size += gd->bd->bi_dram[i].size;
	}
	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
	if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
		return 0;
	else
		return readl(save_addr);
}
#endif

#if defined(CONFIG_SOFT_I2C)
void set_sda (int state)
{
	I2C_ACTIVE;
	I2C_SDA(state);
}

void set_scl (int state)
{
	I2C_SCL(state);
}

int get_sda (void)
{
	I2C_TRISTATE;
	return I2C_READ;
}

int get_scl (void)
{
	return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
}
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
int eeprom_write_enable (unsigned dev_addr, int state)
{
	kw_gpio_set_value(SUEN3_ENV_WP, !state);

	return !kw_gpio_get_value(SUEN3_ENV_WP);
}
#endif
Commit	Line	Data
67fa8c25 HS	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Prafulla Wadaskar <prafulla@marvell.com>
	5	*
	6	* (C) Copyright 2009
	7	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	8	*
	9	* (C) Copyright 2010
	10	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	28	* MA 02110-1301 USA
	29	*/
	30
	31	#include <common.h>
	32	#include <i2c.h>
	33	#include <nand.h>
	34	#include <netdev.h>
	35	#include <miiphy.h>
	36	#include <asm/io.h>
	37	#include <asm/arch/kirkwood.h>
	38	#include <asm/arch/mpp.h>
	39
	40	#include "../common/common.h"
	41
	42	DECLARE_GLOBAL_DATA_PTR;
	43
	44	static int io_dev;
	45	extern I2C_MUX_DEVICE i2c_mux_ident_muxstring (uchar buf);
	46
	47	/* Multi-Purpose Pins Functionality configuration */
	48	u32 kwmpp_config[] = {
	49	MPP0_NF_IO2,
	50	MPP1_NF_IO3,
	51	MPP2_NF_IO4,
	52	MPP3_NF_IO5,
	53	MPP4_NF_IO6,
	54	MPP5_NF_IO7,
	55	MPP6_SYSRST_OUTn,
	56	MPP7_PEX_RST_OUTn,
	57	#if defined(CONFIG_SOFT_I2C)
	58	MPP8_GPIO, /* SDA */
	59	MPP9_GPIO, /* SCL */
	60	#endif
	61	#if defined(CONFIG_HARD_I2C)
	62	MPP8_TW_SDA,
	63	MPP9_TW_SCK,
	64	#endif
65	MPP10_UART0_TXD,
66	MPP11_UART0_RXD,
67	MPP12_GPO, /* Reserved */
68	MPP13_UART1_TXD,
69	MPP14_UART1_RXD,
70	MPP15_GPIO, /* Not used */
71	MPP16_GPIO, /* Not used */
72	MPP17_GPIO, /* Reserved */
73	MPP18_NF_IO0,
74	MPP19_NF_IO1,
75	MPP20_GPIO,
76	MPP21_GPIO,
77	MPP22_GPIO,
78	MPP23_GPIO,
79	MPP24_GPIO,
80	MPP25_GPIO,
81	MPP26_GPIO,
82	MPP27_GPIO,
83	MPP28_GPIO,
84	MPP29_GPIO,
85	MPP30_GPIO,
86	MPP31_GPIO,
87	MPP32_GPIO,
88	MPP33_GPIO,
89	MPP34_GPIO, /* CDL1 (input) */
90	MPP35_GPIO, /* CDL2 (input) */
91	MPP36_GPIO, /* MAIN_IRQ (input) */
92	MPP37_GPIO, /* BOARD_LED */
93	MPP38_GPIO, /* Piggy3 LED[1] */
94	MPP39_GPIO, /* Piggy3 LED[2] */
95	MPP40_GPIO, /* Piggy3 LED[3] */
96	MPP41_GPIO, /* Piggy3 LED[4] */
97	MPP42_GPIO, /* Piggy3 LED[5] */
98	MPP43_GPIO, /* Piggy3 LED[6] */
99	MPP44_GPIO, /* Piggy3 LED[7] */
100	MPP45_GPIO, /* Piggy3 LED[8] */
101	MPP46_GPIO, /* Reserved */
102	MPP47_GPIO, /* Reserved */
103	MPP48_GPIO, /* Reserved */
104	MPP49_GPIO, /* SW_INTOUTn */
105	0
106	};
107
108	int ethernet_present(void)
109	{
110	uchar buf;
111	int ret = 0;
112
113	if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
114	printf ("%s: Error reading Boco\n", __FUNCTION__);
115	return -1;
116	}
117	if ((buf & 0x40) == 0x40) {
118	ret = 1;
119	}
120	return ret;
121	}
122
123	int misc_init_r(void)
124	{
125	I2C_MUX_DEVICE *i2cdev;
126	char *str;
127	int mach_type;
128
129	/* add I2C Bus for I/O Expander */
130	i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
131	io_dev = i2cdev->busid;
132	puts("Piggy:");
133	if (ethernet_present() == 0)
134	puts (" not");
135	puts(" present\n");
136
137	str = getenv("mach_type");
138	if (str != NULL) {
139	mach_type = simple_strtoul(str, NULL, 10);
140	printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
141	gd->bd->bi_arch_number = mach_type;
142	}
143	return 0;
144	}
145
146	int board_init(void)
147	{
148	u32 tmp;
149
150	kirkwood_mpp_conf(kwmpp_config);
151
152	/*
153	* The FLASH_GPIO_PIN switches between using a
154	* NAND or a SPI FLASH. Set this pin on start
155	* to NAND mode.
156	*/
157	tmp = readl(KW_GPIO0_BASE);
158	writel(tmp \| FLASH_GPIO_PIN , KW_GPIO0_BASE);
159	tmp = readl(KW_GPIO0_BASE + 4);
160	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
161	printf("KM: setting NAND mode\n");
162
163	/*
164	* arch number of board
165	*/
166	gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
167
168	/* address of boot parameters */
169	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
170
171	#if defined(CONFIG_SOFT_I2C)
172	/* init the GPIO for I2C Bitbang driver */
173	kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
174	kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
175	kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
176	kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
177	#endif
178	#if defined(CONFIG_SYS_EEPROM_WREN)
179	kw_gpio_set_valid(SUEN3_ENV_WP, 38);
180	kw_gpio_direction_output(SUEN3_ENV_WP, 1);
181	#endif
182	return 0;
183	}
184
185	#if defined(CONFIG_CMD_SF)
54841ab5	186	int do_spi_toggle(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
67fa8c25 HS	187	{
67fa8c25 HS	188	u32 tmp;
47e26b1b WD	189	if (argc < 2)
47e26b1b WD	190	return cmd_usage(cmdtp);
67fa8c25 HS	191
	192	if ((strcmp(argv[1], "off") == 0)) {
	193	printf("SPI FLASH disabled, NAND enabled\n");
	194	/* Multi-Purpose Pins Functionality configuration */
	195	kwmpp_config[0] = MPP0_NF_IO2;
	196	kwmpp_config[1] = MPP1_NF_IO3;
	197	kwmpp_config[2] = MPP2_NF_IO4;
	198	kwmpp_config[3] = MPP3_NF_IO5;
	199
	200	kirkwood_mpp_conf(kwmpp_config);
	201	tmp = readl(KW_GPIO0_BASE);
	202	writel(tmp \| FLASH_GPIO_PIN , KW_GPIO0_BASE);
	203	} else if ((strcmp(argv[1], "on") == 0)) {
	204	printf("SPI FLASH enabled, NAND disabled\n");
	205	/* Multi-Purpose Pins Functionality configuration */
	206	kwmpp_config[0] = MPP0_SPI_SCn;
	207	kwmpp_config[1] = MPP1_SPI_MOSI;
	208	kwmpp_config[2] = MPP2_SPI_SCK;
	209	kwmpp_config[3] = MPP3_SPI_MISO;
	210
	211	kirkwood_mpp_conf(kwmpp_config);
	212	tmp = readl(KW_GPIO0_BASE);
	213	writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
	214	} else {
47e26b1b	215	return cmd_usage(cmdtp);
67fa8c25 HS	216	}
	217
	218	return 0;
	219	}
	220
	221	U_BOOT_CMD(
	222	spitoggle, 2, 0, do_spi_toggle,
	223	"En-/disable SPI FLASH access",
	224	"<on\|off> - Enable (on) or disable (off) SPI FLASH access\n"
	225	);
	226	#endif
	227
ab86f72c	228	#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
67fa8c25 HS	229	int dram_init(void)
	230	{
	231	int i;
	232
	233	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
	234	gd->bd->bi_dram[i].start = kw_sdram_bar(i);
	235	gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
	236	kw_sdram_bs(i));
	237	}
ab86f72c HS	238
	239	return 0;
	240	}
	241	#else
	242	int dram_init(void)
	243	{
	244	/* dram_init must store complete ramsize in gd->ram_size */
	245	/* Fix this */
	246	gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
	247	kw_sdram_bs(0));
67fa8c25 HS	248	return 0;
	249	}
	250
ab86f72c HS	251	void dram_init_banksize(void)
	252	{
	253	int i;
	254
	255	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
	256	gd->bd->bi_dram[i].start = kw_sdram_bar(i);
	257	gd->bd->bi_dram[i].size = kw_sdram_bs(i);
	258	gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
	259	kw_sdram_bs(i));
	260	}
	261	}
	262	#endif
	263
67fa8c25 HS	264	/* Configure and enable MV88E1118 PHY */
	265	void reset_phy(void)
	266	{
	267	char *name = "egiga0";
	268
	269	if (miiphy_set_current_dev(name))
	270	return;
	271
	272	/* reset the phy */
	273	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
	274	}
	275
	276	#if defined(CONFIG_HUSH_INIT_VAR)
	277	int hush_init_var (void)
	278	{
	279	ivm_read_eeprom ();
	280	return 0;
	281	}
	282	#endif
	283
	284	#if defined(CONFIG_BOOTCOUNT_LIMIT)
	285	void bootcount_store (ulong a)
	286	{
	287	volatile ulong *save_addr;
	288	volatile ulong size = 0;
	289	int i;
	290	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
	291	size += gd->bd->bi_dram[i].size;
	292	}
	293	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
	294	writel(a, save_addr);
	295	writel(BOOTCOUNT_MAGIC, &save_addr[1]);
	296	}
	297
	298	ulong bootcount_load (void)
	299	{
	300	volatile ulong *save_addr;
	301	volatile ulong size = 0;
	302	int i;
	303	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
	304	size += gd->bd->bi_dram[i].size;
	305	}
	306	save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
	307	if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
	308	return 0;
	309	else
	310	return readl(save_addr);
	311	}
	312	#endif
	313
	314	#if defined(CONFIG_SOFT_I2C)
	315	void set_sda (int state)
	316	{
	317	I2C_ACTIVE;
	318	I2C_SDA(state);
	319	}
	320
	321	void set_scl (int state)
	322	{
	323	I2C_SCL(state);
	324	}
	325
	326	int get_sda (void)
	327	{
328	I2C_TRISTATE;
329	return I2C_READ;
330	}
331
332	int get_scl (void)
333	{
334	return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
335	}
336	#endif
337
338	#if defined(CONFIG_SYS_EEPROM_WREN)
339	int eeprom_write_enable (unsigned dev_addr, int state)
340	{
341	kw_gpio_set_value(SUEN3_ENV_WP, !state);
342
343	return !kw_gpio_get_value(SUEN3_ENV_WP);
344	}
345	#endif