]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | # SPDX-License-Identifier: GPL-2.0+ |
68d6963c VL |
2 | # |
3 | # (C) Copyright 2010 | |
4 | # Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
5 | # | |
6 | # (C) Copyright 2011 | |
7 | # Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com | |
b1e6c4c3 | 8 | # Refer doc/README.kwbimage for more details about how-to configure |
68d6963c VL |
9 | # and create kirkwood boot image |
10 | # | |
11 | ||
12 | # Boot Media configurations | |
13 | BOOT_FROM spi # Boot from SPI flash | |
14 | ||
15 | DATA 0xFFD10000 0x01112222 # MPP Control 0 Register | |
16 | # bit 3-0: MPPSel0 2, NF_IO[2] | |
17 | # bit 7-4: MPPSel1 2, NF_IO[3] | |
18 | # bit 12-8: MPPSel2 2, NF_IO[4] | |
19 | # bit 15-12: MPPSel3 2, NF_IO[5] | |
20 | # bit 19-16: MPPSel4 1, NF_IO[6] | |
21 | # bit 23-20: MPPSel5 1, NF_IO[7] | |
22 | # bit 27-24: MPPSel6 1, SYSRST_O | |
23 | # bit 31-28: MPPSel7 0, GPO[7] | |
24 | ||
25 | DATA 0xFFD10004 0x03303300 | |
26 | ||
27 | DATA 0xFFD10008 0x00001100 # MPP Control 2 Register | |
28 | # bit 3-0: MPPSel16 0, GPIO[16] | |
29 | # bit 7-4: MPPSel17 0, GPIO[17] | |
30 | # bit 12-8: MPPSel18 1, NF_IO[0] | |
31 | # bit 15-12: MPPSel19 1, NF_IO[1] | |
32 | # bit 19-16: MPPSel20 0, GPIO[20] | |
33 | # bit 23-20: MPPSel21 0, GPIO[21] | |
34 | # bit 27-24: MPPSel22 0, GPIO[22] | |
35 | # bit 31-28: MPPSel23 0, GPIO[23] | |
36 | ||
37 | DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register | |
38 | DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register | |
39 | DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register | |
2472216c HB |
40 | |
41 | # NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! | |
42 | # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage | |
68d6963c VL |
43 | |
44 | #Dram initalization | |
45 | DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register | |
46 | # bit13-0: 0x4E0 (DDR2 clks refresh rate) | |
47 | # bit23-14: zero | |
48 | # bit24: 1= enable exit self refresh mode on DDR access | |
49 | # bit25: 1 required | |
50 | # bit29-26: zero | |
51 | # bit31-30: 01 | |
52 | ||
53 | DATA 0xFFD01404 0x38543000 # DDR Controller Control Low | |
54 | # bit 3-0: 0 reserved | |
55 | # bit 4: 0=addr/cmd in smame cycle | |
56 | # bit 5: 0=clk is driven during self refresh, we don't care for APX | |
57 | # bit 6: 0=use recommended falling edge of clk for addr/cmd | |
58 | # bit14: 0=input buffer always powered up | |
59 | # bit18: 1=cpu lock transaction enabled | |
60 | # bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 | |
61 | # bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM | |
62 | # bit30-28: 3 required | |
63 | # bit31: 0=no additional STARTBURST delay | |
64 | ||
65 | DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1) | |
66 | # bit3-0: TRAS lsbs | |
67 | # bit7-4: TRCD | |
68 | # bit11- 8: TRP | |
69 | # bit15-12: TWR | |
70 | # bit19-16: TWTR | |
71 | # bit20: TRAS msb | |
72 | # bit23-21: 0x0 | |
73 | # bit27-24: TRRD | |
74 | # bit31-28: TRTP | |
75 | ||
76 | DATA 0xFFD0140C 0x00000A3E # DDR Timing (High) | |
77 | # bit6-0: TRFC | |
78 | # bit8-7: TR2R | |
79 | # bit10-9: TR2W | |
80 | # bit12-11: TW2W | |
81 | # bit31-13: zero required | |
82 | ||
83 | DATA 0xFFD01410 0x00000001 # DDR Address Control | |
84 | # bit1-0: 01, Cs0width=x16 | |
85 | # bit3-2: 00, Cs0size=2Gb | |
86 | # bit5-4: 00, Cs2width=nonexistent | |
87 | # bit7-6: 00, Cs1size =nonexistent | |
88 | # bit9-8: 00, Cs2width=nonexistent | |
89 | # bit11-10: 00, Cs2size =nonexistent | |
90 | # bit13-12: 00, Cs3width=nonexistent | |
91 | # bit15-14: 00, Cs3size =nonexistent | |
92 | # bit16: 0, Cs0AddrSel | |
93 | # bit17: 0, Cs1AddrSel | |
94 | # bit18: 0, Cs2AddrSel | |
95 | # bit19: 0, Cs3AddrSel | |
96 | # bit31-20: 0 required | |
97 | ||
98 | DATA 0xFFD01414 0x00000000 # DDR Open Pages Control | |
99 | # bit0: 0, OpenPage enabled | |
100 | # bit31-1: 0 required | |
101 | ||
102 | DATA 0xFFD01418 0x00000000 # DDR Operation | |
103 | # bit3-0: 0x0, DDR cmd | |
104 | # bit31-4: 0 required | |
105 | ||
106 | DATA 0xFFD0141C 0x00000652 # DDR Mode | |
107 | DATA 0xFFD01420 0x00000006 # DDR Extended Mode | |
108 | # bit0: 0, DDR DLL enabled | |
109 | # bit1: 1, DDR drive strenght reduced | |
110 | # bit2: 1, DDR ODT control lsd disabled | |
111 | # bit5-3: 000, required | |
112 | # bit6: 0, DDR ODT control msb disabled | |
113 | # bit9-7: 000, required | |
114 | # bit10: 0, differential DQS enabled | |
115 | # bit11: 0, required | |
116 | # bit12: 0, DDR output buffer enabled | |
117 | # bit31-13: 0 required | |
118 | ||
119 | DATA 0xFFD01424 0x0000F17F # DDR Controller Control High | |
120 | # bit2-0: 111, required | |
121 | # bit3 : 1 , MBUS Burst Chop disabled | |
122 | # bit6-4: 111, required | |
123 | # bit7 : 0 | |
124 | # bit8 : 1 , add a sample stage | |
125 | # bit9 : 0 , no half clock cycle addition to dataout | |
126 | # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals | |
127 | # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh | |
128 | # bit15-12: 1111 required | |
129 | # bit31-16: 0 required | |
130 | ||
131 | DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low | |
132 | # bit3-0 : 0000, required | |
133 | # bit7-4 : 0010, M_ODT assertion 2 cycles after read | |
e947cbc9 | 134 | # bit11-8 : 0101, M_ODT de-assertion 5 cycles after read |
68d6963c VL |
135 | # bit15-12: 0100, internal ODT assertion 4 cycles after read |
136 | # bit19-16: 1000, internal ODT de-assertion 8 cycles after read | |
137 | # bit31-20: 0 , required | |
138 | ||
139 | DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High | |
140 | # bit3-0 : 0001, M_ODT assertion same cycle as write | |
141 | # bit7-4 : 0101, M_ODT de-assertion x cycles after write | |
142 | # bit11-8 : 0100, internal ODT assertion x cycles after write | |
143 | # bit15-12: 1000, internal ODT de-assertion x cycles after write | |
144 | ||
145 | DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 | |
146 | DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size | |
147 | # bit0: 1, Window enabled | |
148 | # bit1: 0, Write Protect disabled | |
149 | # bit3-2: 00, CS0 hit selected | |
150 | # bit23-4: ones, required | |
151 | # bit31-24: 0x0F, Size (i.e. 256MB) | |
152 | ||
153 | DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled | |
154 | DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled | |
155 | DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled | |
156 | ||
157 | DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) | |
158 | # bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 | |
159 | # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 | |
160 | ||
161 | DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) | |
162 | # bit1-0: 00, ODT0 controlled by ODT Control (low) register above | |
163 | # bit3-2: 00, ODT1 controlled by register | |
164 | # bit31-4: zero, required | |
165 | ||
166 | DATA 0xFFD0149C 0x0000F801 # CPU ODT Control | |
167 | # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 | |
168 | # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 | |
169 | # bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr | |
170 | # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm | |
171 | # bit13-12:3, STARTBURST ODT buffer selected, 50 ohm | |
172 | # bit14 :1, STARTBURST ODT enabled | |
173 | # bit15 :1, Use ODT Block | |
174 | ||
175 | DATA 0xFFD01480 0x00000001 # DDR Initialization Control | |
176 | # bit0=1, enable DDR init upon this register write | |
177 | ||
178 | # End of Header extension | |
179 | DATA 0x0 0x0 |