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c591dffe | 1 | /* |
0ddd969a | 2 | * (C) Copyright 2007-2008 |
c591dffe LJ |
3 | * Larry Johnson, lrj@acm.org |
4 | * | |
6433fa20 | 5 | * (C) Copyright 2006-2007 |
c591dffe LJ |
6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
7 | * | |
8 | * (C) Copyright 2006 | |
9 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
6433fa20 | 10 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
c591dffe LJ |
11 | * |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
47ce4a28 | 29 | #include <fdt_support.h> |
c591dffe | 30 | #include <i2c.h> |
47ce4a28 | 31 | #include <libfdt.h> |
c591dffe | 32 | #include <ppc440.h> |
47ce4a28 | 33 | #include <asm/bitops.h> |
3259eeaa | 34 | #include <asm/gpio.h> |
3259eeaa | 35 | #include <asm/io.h> |
6bd91384 | 36 | #include <asm/ppc4xx-uic.h> |
47ce4a28 | 37 | #include <asm/processor.h> |
c591dffe LJ |
38 | |
39 | DECLARE_GLOBAL_DATA_PTR; | |
40 | ||
6d0f6bcf | 41 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
c591dffe LJ |
42 | |
43 | ulong flash_get_size(ulong base, int banknum); | |
44 | ||
6433fa20 LJ |
45 | #if defined(CONFIG_KORAT_PERMANENT) |
46 | void korat_buzzer(int const on) | |
47 | { | |
48 | if (on) { | |
6d0f6bcf JCPV |
49 | out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, |
50 | in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80); | |
6433fa20 | 51 | } else { |
6d0f6bcf JCPV |
52 | out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, |
53 | in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80); | |
6433fa20 LJ |
54 | } |
55 | } | |
56 | #endif | |
57 | ||
c591dffe LJ |
58 | int board_early_init_f(void) |
59 | { | |
6433fa20 LJ |
60 | uint32_t sdr0_pfc1, sdr0_pfc2; |
61 | uint32_t reg; | |
c591dffe LJ |
62 | int eth; |
63 | ||
6433fa20 LJ |
64 | #if defined(CONFIG_KORAT_PERMANENT) |
65 | unsigned mscount; | |
66 | ||
67 | extern void korat_branch_absolute(uint32_t addr); | |
68 | ||
6d0f6bcf | 69 | for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) { |
6433fa20 | 70 | udelay(1000); |
6d0f6bcf | 71 | if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) { |
6433fa20 LJ |
72 | /* This call does not return. */ |
73 | korat_branch_absolute( | |
6d0f6bcf | 74 | CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4); |
6433fa20 LJ |
75 | } |
76 | } | |
77 | korat_buzzer(1); | |
6d0f6bcf | 78 | while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) |
6433fa20 LJ |
79 | udelay(1000); |
80 | ||
81 | korat_buzzer(0); | |
82 | #endif | |
83 | ||
c591dffe LJ |
84 | mtdcr(ebccfga, xbcfg); |
85 | mtdcr(ebccfgd, 0xb8400000); | |
86 | ||
3259eeaa | 87 | /* |
c591dffe | 88 | * Setup the interrupt controller polarities, triggers, etc. |
3259eeaa | 89 | */ |
c591dffe LJ |
90 | mtdcr(uic0sr, 0xffffffff); /* clear all */ |
91 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
92 | mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ | |
93 | mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ | |
94 | mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ | |
95 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ | |
96 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
97 | ||
98 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
99 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
100 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
101 | mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ | |
102 | mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ | |
103 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ | |
104 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
105 | ||
106 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
107 | mtdcr(uic2er, 0x00000000); /* disable all */ | |
108 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ | |
109 | mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ | |
110 | mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ | |
111 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ | |
112 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
113 | ||
6433fa20 LJ |
114 | /* |
115 | * Take sim card reader and CF controller out of reset. Also enable PHY | |
116 | * auto-detect until board-specific PHY resets are available. | |
117 | */ | |
6d0f6bcf | 118 | out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0); |
c591dffe LJ |
119 | |
120 | /* Configure the two Ethernet PHYs. For each PHY, configure for fiber | |
121 | * if the SFP module is present, and for copper if it is not present. | |
122 | */ | |
c591dffe | 123 | for (eth = 0; eth < 2; ++eth) { |
6d0f6bcf | 124 | if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) { |
c591dffe LJ |
125 | /* SFP module not present: configure PHY for copper. */ |
126 | /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ | |
6d0f6bcf JCPV |
127 | out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, |
128 | in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | | |
c591dffe LJ |
129 | 0x06 << (4 * eth)); |
130 | } else { | |
131 | /* SFP module present: configure PHY for fiber and | |
132 | enable output */ | |
6d0f6bcf JCPV |
133 | gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1); |
134 | gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0); | |
c591dffe LJ |
135 | } |
136 | } | |
137 | /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ | |
6d0f6bcf JCPV |
138 | gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1); |
139 | gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1); | |
c591dffe | 140 | |
6433fa20 LJ |
141 | /* Wait 1 ms, then enable Fiber signal detect to PHYs. */ |
142 | udelay(1000); | |
6d0f6bcf JCPV |
143 | out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, |
144 | in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88); | |
6433fa20 LJ |
145 | |
146 | /* select Ethernet (and optionally IIC1) pins */ | |
c591dffe LJ |
147 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
148 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | | |
3259eeaa | 149 | SDR0_PFC1_SELECT_CONFIG_4; |
6433fa20 LJ |
150 | #ifdef CONFIG_I2C_MULTI_BUS |
151 | sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); | |
152 | #endif | |
c591dffe LJ |
153 | mfsdr(SDR0_PFC2, sdr0_pfc2); |
154 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | | |
3259eeaa | 155 | SDR0_PFC2_SELECT_CONFIG_4; |
c591dffe LJ |
156 | mtsdr(SDR0_PFC2, sdr0_pfc2); |
157 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
158 | ||
159 | /* PCI arbiter enabled */ | |
160 | mfsdr(sdr_pci0, reg); | |
161 | mtsdr(sdr_pci0, 0x80000000 | reg); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
6433fa20 LJ |
166 | /* |
167 | * The boot flash on CS0 normally has its write-enable pin disabled, and so will | |
168 | * not respond to CFI commands. This routine therefore fills in the flash | |
169 | * information for the boot flash. (The flash at CS1 operates normally.) | |
170 | */ | |
171 | ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) | |
172 | { | |
173 | uint32_t addr; | |
174 | int i; | |
175 | ||
176 | if (1 != banknum) | |
177 | return 0; | |
178 | ||
6d0f6bcf JCPV |
179 | info->size = CONFIG_SYS_FLASH0_SIZE; |
180 | info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000; | |
6433fa20 LJ |
181 | info->flash_id = 0x01000000; |
182 | info->portwidth = 2; | |
183 | info->chipwidth = 2; | |
184 | info->buffer_size = 32; | |
185 | info->erase_blk_tout = 16384; | |
186 | info->write_tout = 2; | |
187 | info->buffer_write_tout = 5; | |
188 | info->vendor = 2; | |
189 | info->cmd_reset = 0x00F0; | |
190 | info->interface = 2; | |
191 | info->legacy_unlock = 0; | |
192 | info->manufacturer_id = 1; | |
193 | info->device_id = 0x007E; | |
194 | ||
6d0f6bcf | 195 | #if CONFIG_SYS_FLASH0_SIZE == 0x01000000 |
6433fa20 | 196 | info->device_id2 = 0x2101; |
6d0f6bcf | 197 | #elif CONFIG_SYS_FLASH0_SIZE == 0x04000000 |
6433fa20 LJ |
198 | info->device_id2 = 0x2301; |
199 | #else | |
6d0f6bcf | 200 | #error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE |
6433fa20 LJ |
201 | #endif |
202 | ||
203 | info->ext_addr = 0x0040; | |
204 | info->cfi_version = 0x3133; | |
205 | info->cfi_offset = 0x0055; | |
206 | info->addr_unlock1 = 0x00000555; | |
207 | info->addr_unlock2 = 0x000002AA; | |
208 | info->name = "CFI conformant"; | |
209 | for (i = 0, addr = -info->size; | |
210 | i < info->sector_count; | |
211 | ++i, addr += 0x20000) { | |
212 | info->start[i] = addr; | |
213 | info->protect[i] = 0x00; | |
214 | } | |
215 | return 1; | |
216 | } | |
217 | ||
c591dffe LJ |
218 | static int man_data_read(unsigned int addr) |
219 | { | |
220 | /* | |
221 | * Read an octet of data from address "addr" in the manufacturer's | |
222 | * information serial EEPROM, or -1 on error. | |
223 | */ | |
224 | u8 data[2]; | |
225 | ||
226 | if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) || | |
227 | 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) { | |
228 | debug("man_data_read(0x%02X) failed\n", addr); | |
229 | return -1; | |
230 | } | |
231 | debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]); | |
232 | return data[0]; | |
233 | } | |
234 | ||
235 | static unsigned int man_data_field_addr(unsigned int const field) | |
236 | { | |
237 | /* | |
238 | * The manufacturer's information serial EEPROM contains a sequence of | |
239 | * zero-delimited fields. Return the starting address of field "field", | |
240 | * or 0 on error. | |
241 | */ | |
242 | unsigned addr, i; | |
243 | ||
244 | if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1)) | |
245 | /* Only format "A" is currently supported */ | |
246 | return 0; | |
247 | ||
248 | for (addr = 2, i = 1; i < field && addr < 256; ++addr) { | |
249 | if ('\0' == man_data_read(addr)) | |
250 | ++i; | |
251 | } | |
252 | return (addr < 256) ? addr : 0; | |
253 | } | |
254 | ||
255 | static char *man_data_read_field(char s[], unsigned const field, | |
256 | unsigned const length) | |
257 | { | |
258 | /* | |
259 | * Place the null-terminated contents of field "field" of length | |
260 | * "length" from the manufacturer's information serial EEPROM into | |
261 | * string "s[length + 1]" and return a pointer to s, or return 0 on | |
262 | * error. In either case the original contents of s[] is not preserved. | |
263 | */ | |
264 | unsigned addr, i; | |
265 | ||
266 | addr = man_data_field_addr(field); | |
267 | if (0 == addr || addr + length >= 255) | |
268 | return 0; | |
269 | ||
270 | for (i = 0; i < length; ++i) { | |
271 | int const c = man_data_read(addr++); | |
272 | ||
273 | if (c <= 0) | |
274 | return 0; | |
275 | ||
276 | s[i] = (char)c; | |
277 | } | |
278 | if (0 != man_data_read(addr)) | |
279 | return 0; | |
280 | ||
281 | s[i] = '\0'; | |
282 | return s; | |
283 | } | |
284 | ||
285 | static void set_serial_number(void) | |
286 | { | |
287 | /* | |
288 | * If the environmental variable "serial#" is not set, try to set it | |
289 | * from the manufacturer's information serial EEPROM. | |
290 | */ | |
6433fa20 LJ |
291 | char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2]; |
292 | ||
293 | if (getenv("serial#")) | |
294 | return; | |
295 | ||
296 | if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH)) | |
297 | return; | |
298 | ||
299 | s[MAN_INFO_LENGTH] = '-'; | |
300 | if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD, | |
301 | MAN_MAC_ADDR_LENGTH)) | |
302 | return; | |
c591dffe | 303 | |
6433fa20 | 304 | setenv("serial#", s); |
c591dffe LJ |
305 | } |
306 | ||
307 | static void set_mac_addresses(void) | |
308 | { | |
309 | /* | |
310 | * If the environmental variables "ethaddr" and/or "eth1addr" are not | |
311 | * set, try to set them from the manufacturer's information serial | |
312 | * EEPROM. | |
313 | */ | |
6433fa20 LJ |
314 | |
315 | #if MAN_MAC_ADDR_LENGTH % 2 != 0 | |
316 | #error MAN_MAC_ADDR_LENGTH must be an even number | |
317 | #endif | |
318 | ||
319 | char s[(3 * MAN_MAC_ADDR_LENGTH) / 2]; | |
320 | char *src; | |
321 | char *dst; | |
c591dffe LJ |
322 | |
323 | if (0 != getenv("ethaddr") && 0 != getenv("eth1addr")) | |
324 | return; | |
325 | ||
6433fa20 LJ |
326 | if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1, |
327 | MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH)) | |
c591dffe LJ |
328 | return; |
329 | ||
6433fa20 LJ |
330 | for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) { |
331 | *dst++ = *src++; | |
332 | *dst++ = *src++; | |
333 | *dst++ = ':'; | |
334 | } | |
c591dffe LJ |
335 | if (0 == getenv("ethaddr")) |
336 | setenv("ethaddr", s); | |
337 | ||
338 | if (0 == getenv("eth1addr")) { | |
6433fa20 | 339 | ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2]; |
c591dffe LJ |
340 | setenv("eth1addr", s); |
341 | } | |
342 | } | |
343 | ||
c591dffe LJ |
344 | int misc_init_r(void) |
345 | { | |
6433fa20 LJ |
346 | uint32_t pbcr; |
347 | int size_val; | |
348 | uint32_t reg; | |
c591dffe LJ |
349 | unsigned long usb2d0cr = 0; |
350 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
351 | unsigned long sdr0_pfc1; | |
6d0f6bcf | 352 | uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; |
6433fa20 | 353 | char const *const act = getenv("usbact"); |
c591dffe | 354 | |
6433fa20 LJ |
355 | /* |
356 | * Re-do FLASH1 sizing and adjust flash start and offset. | |
357 | */ | |
6d0f6bcf | 358 | gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size; |
c591dffe LJ |
359 | gd->bd->bi_flashoffset = 0; |
360 | ||
6433fa20 | 361 | mtdcr(ebccfga, pb1cr); |
c591dffe | 362 | pbcr = mfdcr(ebccfgd); |
6433fa20 | 363 | size_val = ffs(flash1_size) - 21; |
c591dffe | 364 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
6433fa20 | 365 | mtdcr(ebccfga, pb1cr); |
c591dffe LJ |
366 | mtdcr(ebccfgd, pbcr); |
367 | ||
368 | /* | |
369 | * Re-check to get correct base address | |
370 | */ | |
371 | flash_get_size(gd->bd->bi_flashstart, 0); | |
372 | ||
6433fa20 LJ |
373 | /* |
374 | * Re-do FLASH1 sizing and adjust flash offset to reserve space for | |
375 | * environment | |
376 | */ | |
377 | gd->bd->bi_flashoffset = | |
6d0f6bcf | 378 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR; |
c591dffe | 379 | |
6433fa20 LJ |
380 | mtdcr(ebccfga, pb1cr); |
381 | pbcr = mfdcr(ebccfgd); | |
6d0f6bcf | 382 | size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21; |
6433fa20 LJ |
383 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
384 | mtdcr(ebccfga, pb1cr); | |
385 | mtdcr(ebccfgd, pbcr); | |
386 | ||
387 | /* Monitor protection ON by default */ | |
388 | #if defined(CONFIG_KORAT_PERMANENT) | |
6d0f6bcf JCPV |
389 | (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, |
390 | CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, | |
6433fa20 LJ |
391 | flash_info + 1); |
392 | #else | |
6d0f6bcf JCPV |
393 | (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, |
394 | CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, | |
6433fa20 LJ |
395 | flash_info); |
396 | #endif | |
c591dffe | 397 | /* Env protection ON by default */ |
0e8d1586 JCPV |
398 | (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, |
399 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, | |
6433fa20 | 400 | flash_info); |
0e8d1586 JCPV |
401 | (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, |
402 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, | |
6433fa20 | 403 | flash_info); |
c591dffe LJ |
404 | |
405 | /* | |
406 | * USB suff... | |
407 | */ | |
408 | if (act == NULL || strcmp(act, "hostdev") == 0) { | |
409 | /* SDR Setting */ | |
410 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
411 | mfsdr(SDR0_USB2D0CR, usb2d0cr); | |
412 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
413 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
414 | ||
3259eeaa LJ |
415 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; |
416 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; | |
417 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; | |
418 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; | |
419 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
420 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; | |
421 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
422 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; | |
423 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
424 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; | |
425 | ||
426 | /* | |
427 | * An 8-bit/60MHz interface is the only possible alternative | |
428 | * when connecting the Device to the PHY | |
429 | */ | |
430 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
431 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; | |
432 | ||
433 | /* | |
434 | * To enable the USB 2.0 Device function | |
435 | * through the UTMI interface | |
436 | */ | |
437 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
438 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; | |
439 | ||
440 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
441 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; | |
c591dffe LJ |
442 | |
443 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
444 | mtsdr(SDR0_USB2D0CR, usb2d0cr); | |
445 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
446 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
447 | ||
3259eeaa | 448 | /* clear resets */ |
c591dffe LJ |
449 | udelay(1000); |
450 | mtsdr(SDR0_SRST1, 0x00000000); | |
451 | udelay(1000); | |
452 | mtsdr(SDR0_SRST0, 0x00000000); | |
453 | ||
454 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
455 | ||
456 | } else if (strcmp(act, "dev") == 0) { | |
457 | /*-------------------PATCH-------------------------------*/ | |
458 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
459 | ||
3259eeaa LJ |
460 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; |
461 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; | |
462 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
463 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; | |
464 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
465 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; | |
466 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
467 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; | |
c591dffe LJ |
468 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
469 | ||
470 | udelay(1000); | |
471 | mtsdr(SDR0_SRST1, 0x672c6000); | |
472 | ||
473 | udelay(1000); | |
474 | mtsdr(SDR0_SRST0, 0x00000080); | |
475 | ||
476 | udelay(1000); | |
477 | mtsdr(SDR0_SRST1, 0x60206000); | |
478 | ||
479 | *(unsigned int *)(0xe0000350) = 0x00000001; | |
480 | ||
481 | udelay(1000); | |
482 | mtsdr(SDR0_SRST1, 0x60306000); | |
483 | /*-------------------PATCH-------------------------------*/ | |
484 | ||
485 | /* SDR Setting */ | |
486 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
487 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
488 | mfsdr(SDR0_USB2D0CR, usb2d0cr); | |
489 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
490 | ||
3259eeaa LJ |
491 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; |
492 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; | |
493 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; | |
494 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; | |
495 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
496 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; | |
497 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
498 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; | |
499 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
500 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; | |
c591dffe | 501 | |
3259eeaa LJ |
502 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
503 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; | |
c591dffe | 504 | |
3259eeaa LJ |
505 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
506 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; | |
c591dffe | 507 | |
3259eeaa LJ |
508 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
509 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; | |
c591dffe LJ |
510 | |
511 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
512 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
513 | mtsdr(SDR0_USB2D0CR, usb2d0cr); | |
514 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
515 | ||
3259eeaa | 516 | /* clear resets */ |
c591dffe LJ |
517 | udelay(1000); |
518 | mtsdr(SDR0_SRST1, 0x00000000); | |
519 | udelay(1000); | |
520 | mtsdr(SDR0_SRST0, 0x00000000); | |
521 | ||
522 | printf("USB: Device(int phy)\n"); | |
523 | } | |
524 | ||
3259eeaa | 525 | mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ |
c591dffe LJ |
526 | reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); |
527 | mtsdr(SDR0_SRST1, reg); | |
528 | ||
529 | /* | |
530 | * Clear PLB4A0_ACR[WRP] | |
531 | * This fix will make the MAL burst disabling patch for the Linux | |
532 | * EMAC driver obsolete. | |
533 | */ | |
534 | reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; | |
535 | mtdcr(plb4_acr, reg); | |
536 | ||
537 | set_serial_number(); | |
538 | set_mac_addresses(); | |
6d0f6bcf | 539 | gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1); |
6433fa20 | 540 | |
c591dffe LJ |
541 | return 0; |
542 | } | |
543 | ||
544 | int checkboard(void) | |
545 | { | |
546 | char const *const s = getenv("serial#"); | |
6d0f6bcf | 547 | u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0); |
c591dffe LJ |
548 | |
549 | printf("Board: Korat, Rev. %X", rev); | |
6433fa20 | 550 | if (s) |
c591dffe LJ |
551 | printf(", serial# %s", s); |
552 | ||
6433fa20 | 553 | printf(".\n Ethernet PHY 0: "); |
6d0f6bcf | 554 | if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL)) |
c591dffe LJ |
555 | printf("fiber"); |
556 | else | |
557 | printf("copper"); | |
558 | ||
559 | printf(", PHY 1: "); | |
6d0f6bcf | 560 | if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL)) |
c591dffe LJ |
561 | printf("fiber"); |
562 | else | |
563 | printf("copper"); | |
564 | ||
565 | printf(".\n"); | |
6433fa20 LJ |
566 | #if defined(CONFIG_KORAT_PERMANENT) |
567 | printf(" Executing permanent copy of U-Boot.\n"); | |
568 | #endif | |
569 | return 0; | |
c591dffe LJ |
570 | } |
571 | ||
47ce4a28 LJ |
572 | #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) |
573 | /* | |
574 | * Assign interrupts to PCI devices. | |
575 | */ | |
576 | void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) | |
577 | { | |
6bd91384 | 578 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); |
47ce4a28 LJ |
579 | } |
580 | #endif | |
581 | ||
3259eeaa LJ |
582 | /* |
583 | * pci_pre_init | |
c591dffe | 584 | * |
3259eeaa LJ |
585 | * This routine is called just prior to registering the hose and gives |
586 | * the board the opportunity to check things. Returning a value of zero | |
587 | * indicates that things are bad & PCI initialization should be aborted. | |
c591dffe | 588 | * |
3259eeaa LJ |
589 | * Different boards may wish to customize the pci controller structure |
590 | * (add regions, override default access routines, etc) or perform | |
591 | * certain pre-initialization actions. | |
592 | */ | |
c591dffe LJ |
593 | #if defined(CONFIG_PCI) |
594 | int pci_pre_init(struct pci_controller *hose) | |
595 | { | |
596 | unsigned long addr; | |
597 | ||
3259eeaa LJ |
598 | /* |
599 | * Set priority for all PLB3 devices to 0. | |
600 | * Set PLB3 arbiter to fair mode. | |
601 | */ | |
c591dffe LJ |
602 | mfsdr(sdr_amp1, addr); |
603 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
604 | addr = mfdcr(plb3_acr); | |
605 | mtdcr(plb3_acr, addr | 0x80000000); | |
606 | ||
3259eeaa LJ |
607 | /* |
608 | * Set priority for all PLB4 devices to 0. | |
609 | */ | |
c591dffe LJ |
610 | mfsdr(sdr_amp0, addr); |
611 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
612 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
613 | mtdcr(plb4_acr, addr); | |
614 | ||
3259eeaa LJ |
615 | /* |
616 | * Set Nebula PLB4 arbiter to fair mode. | |
617 | */ | |
c591dffe LJ |
618 | /* Segment0 */ |
619 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
620 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
621 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
622 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
623 | mtdcr(plb0_acr, addr); | |
624 | ||
625 | /* Segment1 */ | |
626 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
627 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
628 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
629 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
630 | mtdcr(plb1_acr, addr); | |
631 | ||
47ce4a28 LJ |
632 | #if defined(CONFIG_PCI_PNP) |
633 | hose->fixup_irq = korat_pci_fixup_irq; | |
634 | #endif | |
635 | ||
c591dffe LJ |
636 | return 1; |
637 | } | |
638 | #endif /* defined(CONFIG_PCI) */ | |
639 | ||
3259eeaa LJ |
640 | /* |
641 | * pci_target_init | |
c591dffe | 642 | * |
3259eeaa LJ |
643 | * The bootstrap configuration provides default settings for the pci |
644 | * inbound map (PIM). But the bootstrap config choices are limited and | |
645 | * may not be sufficient for a given board. | |
646 | */ | |
6d0f6bcf | 647 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) |
c591dffe LJ |
648 | void pci_target_init(struct pci_controller *hose) |
649 | { | |
3259eeaa | 650 | /* |
c591dffe | 651 | * Set up Direct MMIO registers |
3259eeaa LJ |
652 | */ |
653 | /* | |
654 | * PowerPC440EPX PCI Master configuration. | |
655 | * Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
6433fa20 LJ |
656 | * PLB address 0x80000000-0xBFFFFFFF |
657 | * ==> PCI address 0x80000000-0xBFFFFFFF | |
3259eeaa LJ |
658 | * Use byte reversed out routines to handle endianess. |
659 | * Make this region non-prefetchable. | |
660 | */ | |
661 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ | |
662 | /* - disabled b4 setting */ | |
6d0f6bcf | 663 | out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ |
6433fa20 | 664 | out32r(PCIX0_PMM0PCILA, |
6d0f6bcf | 665 | CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
c591dffe | 666 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
3259eeaa LJ |
667 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ |
668 | /* and enable region */ | |
c591dffe | 669 | |
3259eeaa LJ |
670 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ |
671 | /* - disabled b4 setting */ | |
6433fa20 | 672 | out32r(PCIX0_PMM1LA, |
6d0f6bcf | 673 | CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ |
6433fa20 | 674 | out32r(PCIX0_PMM1PCILA, |
6d0f6bcf | 675 | CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ |
c591dffe | 676 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
3259eeaa LJ |
677 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ |
678 | /* and enable region */ | |
c591dffe LJ |
679 | |
680 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
3259eeaa LJ |
681 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ |
682 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
683 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
c591dffe | 684 | |
3259eeaa | 685 | /* |
c591dffe | 686 | * Set up Configuration registers |
3259eeaa | 687 | */ |
c591dffe LJ |
688 | |
689 | /* Program the board's subsystem id/vendor id */ | |
690 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
6d0f6bcf JCPV |
691 | CONFIG_SYS_PCI_SUBSYS_VENDORID); |
692 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); | |
c591dffe LJ |
693 | |
694 | /* Configure command register as bus master */ | |
695 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
696 | ||
697 | /* 240nS PCI clock */ | |
698 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
699 | ||
700 | /* No error reporting */ | |
701 | pci_write_config_word(0, PCI_ERREN, 0); | |
702 | ||
703 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
704 | ||
3259eeaa LJ |
705 | /* |
706 | * Set up Configuration registers for on-board NEC uPD720101 USB | |
707 | * controller. | |
708 | */ | |
c591dffe LJ |
709 | pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020); |
710 | } | |
6d0f6bcf | 711 | #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |
c591dffe | 712 | |
6d0f6bcf | 713 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) |
c591dffe LJ |
714 | void pci_master_init(struct pci_controller *hose) |
715 | { | |
716 | unsigned short temp_short; | |
717 | ||
3259eeaa LJ |
718 | /* |
719 | * Write the PowerPC440 EP PCI Configuration regs. | |
720 | * Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
721 | * Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
722 | */ | |
c591dffe LJ |
723 | pci_read_config_word(0, PCI_COMMAND, &temp_short); |
724 | pci_write_config_word(0, PCI_COMMAND, | |
725 | temp_short | PCI_COMMAND_MASTER | | |
726 | PCI_COMMAND_MEMORY); | |
727 | } | |
728 | #endif | |
729 | ||
3259eeaa LJ |
730 | /* |
731 | * is_pci_host | |
c591dffe | 732 | * |
3259eeaa LJ |
733 | * This routine is called to determine if a pci scan should be |
734 | * performed. With various hardware environments (especially cPCI and | |
735 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
736 | * bit in the strap register, or generic host/adapter assumptions. | |
c591dffe | 737 | * |
3259eeaa LJ |
738 | * Rather than hard-code a bad assumption in the general 440 code, the |
739 | * 440 pci code requires the board to decide at runtime. | |
c591dffe | 740 | * |
3259eeaa LJ |
741 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
742 | */ | |
c591dffe LJ |
743 | #if defined(CONFIG_PCI) |
744 | int is_pci_host(struct pci_controller *hose) | |
745 | { | |
746 | /* Korat is always configured as host. */ | |
747 | return (1); | |
748 | } | |
3259eeaa | 749 | #endif /* defined(CONFIG_PCI) */ |
c591dffe LJ |
750 | |
751 | #if defined(CONFIG_POST) | |
752 | /* | |
753 | * Returns 1 if keys pressed to start the power-on long-running tests | |
754 | * Called from board_init_f(). | |
755 | */ | |
756 | int post_hotkeys_pressed(void) | |
757 | { | |
3259eeaa | 758 | return 0; /* No hotkeys supported */ |
c591dffe | 759 | } |
3259eeaa | 760 | #endif /* CONFIG_POST */ |
47ce4a28 LJ |
761 | |
762 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
763 | void ft_board_setup(void *blob, bd_t *bd) | |
764 | { | |
765 | u32 val[4]; | |
766 | int rc; | |
767 | ||
768 | ft_cpu_setup(blob, bd); | |
769 | ||
770 | /* Fixup NOR mapping */ | |
771 | val[0] = 1; /* chip select number */ | |
772 | val[1] = 0; /* always 0 */ | |
773 | val[2] = gd->bd->bi_flashstart; | |
6d0f6bcf | 774 | val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; |
47ce4a28 LJ |
775 | rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", |
776 | val, sizeof(val), 1); | |
777 | if (rc) | |
778 | printf("Unable to update property NOR mapping, err=%s\n", | |
779 | fdt_strerror(rc)); | |
780 | } | |
781 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |