[people/ms/u-boot.git] / board / kup / kup4k / kup4k.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8xx.h>
#include "../common/kup.h"
#ifdef CONFIG_KUP4K_LOGO
   #include "s1d13706.h"
#endif

#undef DEBUG
#ifdef  DEBUG
# define debugk(fmt,args...)    printf(fmt ,##args)
#else
# define debugk(fmt,args...)
#endif

typedef struct {
	volatile unsigned char *VmemAddr;
	volatile unsigned char *RegAddr;
} FB_INFO_S1D13xxx;


/* ------------------------------------------------------------------------- */

#if 0
static long int dram_size (long int, long int *, long int);
#endif

#ifdef CONFIG_KUP4K_LOGO
void lcd_logo(bd_t *bd);
#endif


/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
	0x1FF77C47, /* last */

	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */

	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 */
	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x7FFFFC07, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	uchar *latch,rev,mod;

	/*
	 * Init ChipSelect #4 (CAN + HW-Latch)
	 */
	immap->im_memctl.memc_or4 = 0xFFFF8926;
	immap->im_memctl.memc_br4 = 0x90000401;

	latch=(uchar *)0x90000200;
	rev = (*latch & 0xF8) >> 3;
	mod=(*latch & 0x03);
	printf ("Board: KUP4K Rev %d.%d SN: %s\n",rev,mod,getenv("ethaddr"));
	return (0);
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size_b0 = 0;
	long int size_b1 = 0;
	long int size_b2 = 0;

	upmconfig (UPMA, (uint *) sdram_table,
			 sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CFG_MPTPR;

	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */
/*	memctl->memc_or1 = CFG_OR1_PRELIM;	*/
/*	memctl->memc_br1 = CFG_BR1_PRELIM;	*/

/*	memctl->memc_or2 = CFG_OR2_PRELIM;	*/
/*	memctl->memc_br2 = CFG_BR2_PRELIM;	*/


	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
	udelay (1);
	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
	udelay (1);
	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
	udelay (1);

	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
	udelay (1);
	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
	udelay (1);
	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
	udelay (1);

	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
	udelay (1);
	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
	udelay (1);
	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
	udelay (1);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
	udelay (1000);

#if 0							/* 3 x 8MB */
	size_b0 = 0x00800000;
	size_b1 = 0x00800000;
	size_b2 = 0x00800000;
	memctl->memc_mptpr = CFG_MPTPR;
	udelay (1000);
	memctl->memc_or1 = 0xFF800A00;
	memctl->memc_br1 = 0x00000081;
	memctl->memc_or2 = 0xFF000A00;
	memctl->memc_br2 = 0x00800081;
	memctl->memc_or3 = 0xFE000A00;
	memctl->memc_br3 = 0x01000081;
#else							/* 3 x 16 MB */
	size_b0 = 0x01000000;
	size_b1 = 0x01000000;
	size_b2 = 0x01000000;
	memctl->memc_mptpr = CFG_MPTPR;
	udelay (1000);
	memctl->memc_or1 = 0xFF000A00;
	memctl->memc_br1 = 0x00000081;
	memctl->memc_or2 = 0xFE000A00;
	memctl->memc_br2 = 0x01000081;
	memctl->memc_or3 = 0xFC000A00;
	memctl->memc_br3 = 0x02000081;
#endif

	udelay (10000);

	return (size_b0 + size_b1 + size_b2);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */
#if 0
static long int dram_size (long int mamr_value, long int *base,
						   long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile long int *addr;
	ulong cnt, val;
	ulong save[32];				/* to make test non-destructive */
	unsigned char i = 0;

	memctl->memc_mamr = mamr_value;

	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
		addr = base + cnt;		/* pointer arith! */

		save[i++] = *addr;
		*addr = ~cnt;
	}

	/* write 0 to base address */
	addr = base;
	save[i] = *addr;
	*addr = 0;

	/* check at base address */
	if ((val = *addr) != 0) {
		*addr = save[i];
		return (0);
	}

	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
		addr = base + cnt;		/* pointer arith! */

		val = *addr;
		*addr = save[--i];

		if (val != (~cnt)) {
			return (cnt * sizeof (long));
		}
	}
	return (maxsize);
}
#endif

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_STATUS_LED
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
#endif
#ifdef CONFIG_KUP4K_LOGO
	bd_t *bd = gd->bd;

	lcd_logo (bd);
#endif							/* CONFIG_KUP4K_LOGO */
#ifdef CONFIG_IDE_LED
	/* Configure PA8 as output port */
	immap->im_ioport.iop_padir |= 0x80;
	immap->im_ioport.iop_paodr |= 0x80;
	immap->im_ioport.iop_papar &= ~0x80;
	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
#endif
	setenv("hw","4k");
	poweron_key();
	return (0);
}

#ifdef CONFIG_KUP4K_LOGO


void lcd_logo (bd_t * bd)
{
	FB_INFO_S1D13xxx fb_info;
	S1D_INDEX s1dReg;
	S1D_VALUE s1dValue;
	volatile immap_t *immr = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl;
	ushort i;
	uchar *fb;
	int rs, gs, bs;
	int r = 8, g = 8, b = 4;
	int r1, g1, b1;
	int n;
	uchar tmp[64];		/* long enough for environment variables */
	int tft = 0;

	immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
	immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
	immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM);	/* set to 0 = enabled */
	immr->im_cpm.cp_pbdir |= (PB_LCD_PWM);

/*----------------------------------------------------------------------------- */
/* Initialize the chip and the frame buffer driver. */
/*----------------------------------------------------------------------------- */
	memctl = &immr->im_memctl;


	/*
	 * Init ChipSelect #5 (S1D13768)
	 */
	memctl->memc_or5 = 0xFFC007F0;	/* 4 MB  17 WS or externel TA */
	memctl->memc_br5 = 0x80080801;	/* Start at 0x80080000 */

	fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
	fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);

	if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
	    || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
		printf ("Warning:LCD Controller S1D13706 not found\n");
		setenv ("lcd", "none");
		return;
	}


	for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
		s1dReg = aS1DRegs_prelimn[i].Index;
		s1dValue = aS1DRegs_prelimn[i].Value;
		debugk ("s13768 reg: %02x value: %02x\n",
			aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
		((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
			s1dValue;
	}


	n = getenv_r ("lcd", tmp, sizeof (tmp));
	if (n > 0) {
		if (!strcmp ("tft", tmp))
			tft = 1;
		else
			tft = 0;
	}
#if 0
	if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
		tft = 0;
	else
		tft = 1;
#endif

	debugk ("Port=0x%02x -> TFT=%d\n", tft,
		((S1D_VALUE *) fb_info.RegAddr)[0xAC]);

	/* init controller */
	if (!tft) {
		for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
			s1dReg = aS1DRegs_stn[i].Index;
			s1dValue = aS1DRegs_stn[i].Value;
			debugk ("s13768 reg: %02x value: %02x\n",
				aS1DRegs_stn[i].Index,
				aS1DRegs_stn[i].Value);
			((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
				s1dValue;
		}
		n = getenv_r ("contrast", tmp, sizeof (tmp));
		((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
			(n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
		switch (bd->bi_busfreq) {
		case 40000000:
			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
			break;
		case 48000000:
			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
			break;
		default:
			printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
		case 64000000:
			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
			break;
		}
		/*   setenv("lcd","stn"); */
	} else {
		for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
			s1dReg = aS1DRegs_tft[i].Index;
			s1dValue = aS1DRegs_tft[i].Value;
			debugk ("s13768 reg: %02x value: %02x\n",
				aS1DRegs_tft[i].Index,
				aS1DRegs_tft[i].Value);
			((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
				s1dValue;
		}

		switch (bd->bi_busfreq) {
		default:
			printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
		case 40000000:
			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
			break;
		}
		/* setenv("lcd","tft"); */
	}

	/* create and set colormap */
	rs = 256 / (r - 1);
	gs = 256 / (g - 1);
	bs = 256 / (b - 1);
	for (i = 0; i < 256; i++) {
		r1 = (rs * ((i / (g * b)) % r)) * 255;
		g1 = (gs * ((i / b) % g)) * 255;
		b1 = (bs * ((i) % b)) * 255;
		debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
		S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
				   (b1 >> 4));
	}

	/* copy bitmap */
	fb = (char *) (fb_info.VmemAddr);
	memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
}
#endif	/* CONFIG_KUP4K_LOGO */
Commit	Line	Data
56f94be3	1	/*
0608e04d	2	* (C) Copyright 2000-2004
56f94be3 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <mpc8xx.h>
0608e04d	27	#include "../common/kup.h"
56f94be3 WD	28	#ifdef CONFIG_KUP4K_LOGO
	29	#include "s1d13706.h"
	30	#endif
	31
0608e04d WD	32	#undef DEBUG
	33	#ifdef DEBUG
	34	# define debugk(fmt,args...) printf(fmt ,##args)
	35	#else
	36	# define debugk(fmt,args...)
	37	#endif
	38
	39	typedef struct {
	40	volatile unsigned char *VmemAddr;
	41	volatile unsigned char *RegAddr;
	42	} FB_INFO_S1D13xxx;
56f94be3	43
56f94be3 WD	44
	45	/* ------------------------------------------------------------------------- */
	46
	47	#if 0
	48	static long int dram_size (long int, long int *, long int);
	49	#endif
	50
	51	#ifdef CONFIG_KUP4K_LOGO
0608e04d	52	void lcd_logo(bd_t *bd);
56f94be3 WD	53	#endif
56f94be3 WD	54
0608e04d	55
56f94be3 WD	56	/* ------------------------------------------------------------------------- */
	57
	58	#define _NOT_USED_ 0xFFFFFFFF
	59
0608e04d	60	const uint sdram_table[] = {
56f94be3 WD	61	/*
	62	* Single Read. (Offset 0 in UPMA RAM)
	63	*/
682011ff	64	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
56f94be3 WD	65	0x1FF77C47, /* last */
	66
	67	/*
	68	* SDRAM Initialization (offset 5 in UPMA RAM)
	69	*
	70	* This is no UPM entry point. The following definition uses
	71	* the remaining space to establish an initialization
	72	* sequence, which is executed by a RUN command.
	73	*
	74	*/
682011ff	75	0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
56f94be3 WD	76
	77	/*
	78	* Burst Read. (Offset 8 in UPMA RAM)
	79	*/
682011ff WD	80	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
682011ff WD	81	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
56f94be3 WD	82	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	83	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	84
	85	/*
	86	* Single Write. (Offset 18 in UPMA RAM)
	87	*/
682011ff	88	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
56f94be3 WD	89	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	90
	91	/*
	92	* Burst Write. (Offset 20 in UPMA RAM)
	93	*/
682011ff WD	94	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
	95	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
	96	_NOT_USED_,
56f94be3 WD	97	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	98	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	99
	100	/*
	101	* Refresh (Offset 30 in UPMA RAM)
	102	*/
682011ff WD	103	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	104	0xFFFFFC84, 0xFFFFFC07, /* last */
	105	_NOT_USED_, _NOT_USED_,
56f94be3 WD	106	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	107
	108	/*
	109	* Exception. (Offset 3c in UPMA RAM)
	110	*/
	111	0x7FFFFC07, /* last */
	112	_NOT_USED_, _NOT_USED_, _NOT_USED_,
	113	};
	114
	115	/* ------------------------------------------------------------------------- */
	116
	117
	118	/*
	119	* Check Board Identity:
	120	*/
	121
	122	int checkboard (void)
	123	{
0608e04d WD	124	volatile immap_t immap = (immap_t ) CFG_IMMR;
0608e04d WD	125	uchar *latch,rev,mod;
56f94be3	126
0608e04d WD	127	/*
	128	* Init ChipSelect #4 (CAN + HW-Latch)
	129	*/
	130	immap->im_memctl.memc_or4 = 0xFFFF8926;
	131	immap->im_memctl.memc_br4 = 0x90000401;
	132
	133	latch=(uchar *)0x90000200;
	134	rev = (*latch & 0xF8) >> 3;
	135	mod=(*latch & 0x03);
	136	printf ("Board: KUP4K Rev %d.%d SN: %s\n",rev,mod,getenv("ethaddr"));
56f94be3 WD	137	return (0);
	138	}
	139
	140	/* ------------------------------------------------------------------------- */
	141
	142	long int initdram (int board_type)
	143	{
682011ff WD	144	volatile immap_t immap = (immap_t ) CFG_IMMR;
	145	volatile memctl8xx_t *memctl = &immap->im_memctl;
	146	long int size_b0 = 0;
	147	long int size_b1 = 0;
	148	long int size_b2 = 0;
56f94be3	149
682011ff WD	150	upmconfig (UPMA, (uint *) sdram_table,
682011ff WD	151	sizeof (sdram_table) / sizeof (uint));
56f94be3	152
682011ff WD	153	/*
	154	* Preliminary prescaler for refresh (depends on number of
	155	* banks): This value is selected for four cycles every 62.4 us
	156	* with two SDRAM banks or four cycles every 31.2 us with one
	157	* bank. It will be adjusted after memory sizing.
	158	*/
	159	memctl->memc_mptpr = CFG_MPTPR;
56f94be3	160
682011ff	161	memctl->memc_mar = 0x00000088;
56f94be3	162
682011ff WD	163	/*
	164	* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
	165	* preliminary addresses - these have to be modified after the
	166	* SDRAM size has been determined.
	167	*/
	168	/* memctl->memc_or1 = CFG_OR1_PRELIM; */
	169	/* memctl->memc_br1 = CFG_BR1_PRELIM; */
	170
	171	/* memctl->memc_or2 = CFG_OR2_PRELIM; */
	172	/* memctl->memc_br2 = CFG_BR2_PRELIM; */
56f94be3	173
56f94be3	174
682011ff	175	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
56f94be3	176
682011ff	177	udelay (200);
56f94be3	178
682011ff	179	/* perform SDRAM initializsation sequence */
56f94be3	180
682011ff WD	181	memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
	182	udelay (1);
	183	memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
	184	udelay (1);
	185	memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
	186	udelay (1);
56f94be3	187
682011ff WD	188	memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
	189	udelay (1);
	190	memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
	191	udelay (1);
	192	memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
	193	udelay (1);
56f94be3	194
682011ff WD	195	memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
	196	udelay (1);
	197	memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
	198	udelay (1);
	199	memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
	200	udelay (1);
56f94be3	201
682011ff WD	202	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
682011ff WD	203	udelay (1000);
56f94be3	204
682011ff WD	205	#if 0 /* 3 x 8MB */
	206	size_b0 = 0x00800000;
	207	size_b1 = 0x00800000;
	208	size_b2 = 0x00800000;
56f94be3	209	memctl->memc_mptpr = CFG_MPTPR;
682011ff	210	udelay (1000);
56f94be3 WD	211	memctl->memc_or1 = 0xFF800A00;
56f94be3 WD	212	memctl->memc_br1 = 0x00000081;
682011ff WD	213	memctl->memc_or2 = 0xFF000A00;
682011ff WD	214	memctl->memc_br2 = 0x00800081;
56f94be3 WD	215	memctl->memc_or3 = 0xFE000A00;
56f94be3 WD	216	memctl->memc_br3 = 0x01000081;
682011ff WD	217	#else /* 3 x 16 MB */
	218	size_b0 = 0x01000000;
	219	size_b1 = 0x01000000;
	220	size_b2 = 0x01000000;
	221	memctl->memc_mptpr = CFG_MPTPR;
	222	udelay (1000);
	223	memctl->memc_or1 = 0xFF000A00;
	224	memctl->memc_br1 = 0x00000081;
	225	memctl->memc_or2 = 0xFE000A00;
	226	memctl->memc_br2 = 0x01000081;
	227	memctl->memc_or3 = 0xFC000A00;
	228	memctl->memc_br3 = 0x02000081;
	229	#endif
56f94be3	230
682011ff	231	udelay (10000);
56f94be3	232
682011ff	233	return (size_b0 + size_b1 + size_b2);
56f94be3 WD	234	}
	235
	236	/* ------------------------------------------------------------------------- */
	237
	238	/*
	239	* Check memory range for valid RAM. A simple memory test determines
	240	* the actually available RAM size between addresses `base' and
	241	* `base + maxsize'. Some (not all) hardware errors are detected:
	242	* - short between address lines
	243	* - short between data lines
	244	*/
	245	#if 0
682011ff WD	246	static long int dram_size (long int mamr_value, long int *base,
682011ff WD	247	long int maxsize)
56f94be3	248	{
682011ff WD	249	volatile immap_t immap = (immap_t ) CFG_IMMR;
682011ff WD	250	volatile memctl8xx_t *memctl = &immap->im_memctl;
0608e04d WD	251	volatile long int *addr;
	252	ulong cnt, val;
	253	ulong save[32]; /* to make test non-destructive */
	254	unsigned char i = 0;
56f94be3	255
682011ff	256	memctl->memc_mamr = mamr_value;
56f94be3	257
0608e04d WD	258	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
	259	addr = base + cnt; /* pointer arith! */
	260
	261	save[i++] = *addr;
	262	*addr = ~cnt;
	263	}
	264
	265	/* write 0 to base address */
	266	addr = base;
	267	save[i] = *addr;
	268	*addr = 0;
	269
	270	/* check at base address */
	271	if ((val = *addr) != 0) {
	272	*addr = save[i];
	273	return (0);
	274	}
	275
	276	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
	277	addr = base + cnt; /* pointer arith! */
	278
	279	val = *addr;
	280	*addr = save[--i];
	281
	282	if (val != (~cnt)) {
	283	return (cnt * sizeof (long));
	284	}
	285	}
	286	return (maxsize);
56f94be3 WD	287	}
	288	#endif
	289
	290	int misc_init_r (void)
	291	{
	292	DECLARE_GLOBAL_DATA_PTR;
	293
1f53a416	294	#ifdef CONFIG_STATUS_LED
682011ff	295	volatile immap_t immap = (immap_t ) CFG_IMMR;
1f53a416	296	#endif
56f94be3 WD	297	#ifdef CONFIG_KUP4K_LOGO
	298	bd_t *bd = gd->bd;
	299
682011ff WD	300	lcd_logo (bd);
682011ff WD	301	#endif /* CONFIG_KUP4K_LOGO */
1f53a416 WD	302	#ifdef CONFIG_IDE_LED
	303	/* Configure PA8 as output port */
	304	immap->im_ioport.iop_padir \|= 0x80;
	305	immap->im_ioport.iop_paodr \|= 0x80;
	306	immap->im_ioport.iop_papar &= ~0x80;
682011ff	307	immap->im_ioport.iop_padat \|= 0x80; /* turn it off */
1f53a416	308	#endif
0608e04d WD	309	setenv("hw","4k");
0608e04d WD	310	poweron_key();
682011ff	311	return (0);
56f94be3 WD	312	}
	313
	314	#ifdef CONFIG_KUP4K_LOGO
56f94be3	315
682011ff	316
682011ff WD	317	void lcd_logo (bd_t * bd)
682011ff WD	318	{
682011ff WD	319	FB_INFO_S1D13xxx fb_info;
	320	S1D_INDEX s1dReg;
	321	S1D_VALUE s1dValue;
	322	volatile immap_t immr = (immap_t ) CFG_IMMR;
	323	volatile memctl8xx_t *memctl;
56f94be3 WD	324	ushort i;
56f94be3 WD	325	uchar *fb;
682011ff WD	326	int rs, gs, bs;
	327	int r = 8, g = 8, b = 4;
	328	int r1, g1, b1;
0608e04d WD	329	int n;
	330	uchar tmp[64]; /* long enough for environment variables */
	331	int tft = 0;
682011ff	332
0608e04d WD	333	immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
	334	immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
	335	immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */
	336	immr->im_cpm.cp_pbdir \|= (PB_LCD_PWM);
56f94be3 WD	337
56f94be3 WD	338	/----------------------------------------------------------------------------- /
56f94be3	339	/* Initialize the chip and the frame buffer driver. */
56f94be3	340	/----------------------------------------------------------------------------- /
0608e04d	341	memctl = &immr->im_memctl;
56f94be3	342
56f94be3	343
0608e04d WD	344	/*
	345	* Init ChipSelect #5 (S1D13768)
	346	*/
	347	memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */
	348	memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
56f94be3	349
682011ff WD	350	fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
682011ff WD	351	fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
56f94be3	352
682011ff	353	if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
0608e04d	354	\|\| (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
682011ff	355	printf ("Warning:LCD Controller S1D13706 not found\n");
0608e04d	356	setenv ("lcd", "none");
682011ff WD	357	return;
682011ff WD	358	}
56f94be3	359
0608e04d WD	360
	361	for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
	362	s1dReg = aS1DRegs_prelimn[i].Index;
	363	s1dValue = aS1DRegs_prelimn[i].Value;
	364	debugk ("s13768 reg: %02x value: %02x\n",
	365	aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
682011ff	366	((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
0608e04d	367	s1dValue;
682011ff	368	}
56f94be3	369
0608e04d WD	370
	371	n = getenv_r ("lcd", tmp, sizeof (tmp));
	372	if (n > 0) {
	373	if (!strcmp ("tft", tmp))
	374	tft = 1;
	375	else
	376	tft = 0;
56f94be3	377	}
56f94be3	378	#if 0
0608e04d WD	379	if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
	380	tft = 0;
	381	else
	382	tft = 1;
56f94be3 WD	383	#endif
56f94be3 WD	384
0608e04d WD	385	debugk ("Port=0x%02x -> TFT=%d\n", tft,
	386	((S1D_VALUE *) fb_info.RegAddr)[0xAC]);
	387
	388	/* init controller */
	389	if (!tft) {
	390	for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
	391	s1dReg = aS1DRegs_stn[i].Index;
	392	s1dValue = aS1DRegs_stn[i].Value;
	393	debugk ("s13768 reg: %02x value: %02x\n",
	394	aS1DRegs_stn[i].Index,
	395	aS1DRegs_stn[i].Value);
	396	((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
	397	s1dValue;
	398	}
	399	n = getenv_r ("contrast", tmp, sizeof (tmp));
	400	((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
	401	(n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
	402	switch (bd->bi_busfreq) {
	403	case 40000000:
	404	((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
	405	((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
	406	break;
	407	case 48000000:
	408	((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
	409	((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
	410	break;
	411	default:
	412	printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
	413	case 64000000:
	414	((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
	415	((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
	416	break;
	417	}
	418	/* setenv("lcd","stn"); */
	419	} else {
	420	for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
	421	s1dReg = aS1DRegs_tft[i].Index;
	422	s1dValue = aS1DRegs_tft[i].Value;
	423	debugk ("s13768 reg: %02x value: %02x\n",
	424	aS1DRegs_tft[i].Index,
	425	aS1DRegs_tft[i].Value);
	426	((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
	427	s1dValue;
	428	}
	429
	430	switch (bd->bi_busfreq) {
	431	default:
	432	printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
	433	case 40000000:
	434	((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
	435	((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
	436	break;
	437	}
	438	/* setenv("lcd","tft"); */
	439	}
682011ff WD	440
	441	/* create and set colormap */
	442	rs = 256 / (r - 1);
	443	gs = 256 / (g - 1);
	444	bs = 256 / (b - 1);
	445	for (i = 0; i < 256; i++) {
	446	r1 = (rs * ((i / (g * b)) % r)) * 255;
	447	g1 = (gs * ((i / b) % g)) * 255;
	448	b1 = (bs * ((i) % b)) * 255;
0608e04d	449	debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
682011ff	450	S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
0608e04d	451	(b1 >> 4));
682011ff	452	}
56f94be3	453
682011ff WD	454	/* copy bitmap */
	455	fb = (char *) (fb_info.VmemAddr);
	456	memcpy (fb, (uchar ) CONFIG_KUP4K_LOGO, 320 240);
56f94be3	457	}
0608e04d	458	#endif /* CONFIG_KUP4K_LOGO */