[people/ms/u-boot.git] / board / kup4k / kup4k.c

/*
 * (C) Copyright 2000, 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8xx.h>
#ifdef CONFIG_KUP4K_LOGO
   #include "s1d13706.h"
#endif


typedef struct
{
    volatile unsigned char *VmemAddr;
    volatile unsigned char *RegAddr;
}FB_INFO_S1D13xxx;

/* ------------------------------------------------------------------------- */

#if 0
static long int dram_size (long int, long int *, long int);
#endif

#ifdef CONFIG_KUP4K_LOGO
   void lcd_logo(bd_t *bd);
#endif

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint sdram_table[] =
{
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x1F07FC04,
	0xEEAEFC04,
	0x11ADFC04,
	0xEFBBBC00,
	0x1FF77C47, /* last */

	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
	0x1FF77C35,
	0xEFEABC34,
	0x1FB57C35,  /* last */

	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0x1F07FC04,
	0xEEAEFC04,
	0x10ADFC04,
	0xF0AFFC00,
	0xF0AFFC00,
	0xF1AFFC00,
	0xEFBBBC00,
	0x1FF77C47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x1F27FC04,
	0xEEAEBC00,
	0x01B93C04,
    0x1FF77C47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x1F07FC04,
	0xEEAEBC00,
	0x10AD7C00,
	0xF0AFFC00,
	0xF0AFFC00,
	0xE1BBBC04,
	0x1FF77C47, /* last */
    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 */
	0x1FF5FC84,
	0xFFFFFC04,
	0xFFFFFC04,
	0xFFFFFC04,
	0xFFFFFC84,
	0xFFFFFC07, /* last */
	_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x7FFFFC07, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 */

int checkboard (void)
{

	printf ("### No HW ID - assuming KUP4K-Color\n");
	return (0);
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immap->im_memctl;
    long int size_b0 = 0;
    long int size_b1 = 0;
    long int size_b2 = 0;

    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));

    /*
     * Preliminary prescaler for refresh (depends on number of
     * banks): This value is selected for four cycles every 62.4 us
     * with two SDRAM banks or four cycles every 31.2 us with one
     * bank. It will be adjusted after memory sizing.
     */
    memctl->memc_mptpr = CFG_MPTPR;

    memctl->memc_mar  = 0x00000088;

    /*
     * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
     * preliminary addresses - these have to be modified after the
     * SDRAM size has been determined.
     */
/*    memctl->memc_or1 = CFG_OR1_PRELIM;	*/
/*    memctl->memc_br1 = CFG_BR1_PRELIM;	*/
 
/*	memctl->memc_or2 = CFG_OR2_PRELIM;	*/
/*	memctl->memc_br2 = CFG_BR2_PRELIM;	*/


    memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */

    udelay(200);

    /* perform SDRAM initializsation sequence */

    memctl->memc_mcr  = 0x80002105;	/* SDRAM bank 0 */
    udelay(1);
    memctl->memc_mcr  = 0x80002830;	/* SDRAM bank 0 - execute twice */
    udelay(1);
    memctl->memc_mcr  = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
    udelay(1);

	memctl->memc_mcr  = 0x80004105;	/* SDRAM bank 1 */
	udelay(1);
	memctl->memc_mcr  = 0x80004830;	/* SDRAM bank 1 - execute twice */
	udelay(1);
    memctl->memc_mcr  = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
    udelay(1);

	memctl->memc_mcr  = 0x80006105;	/* SDRAM bank 2 */
	udelay(1);
	memctl->memc_mcr  = 0x80006830;	/* SDRAM bank 2 - execute twice */
	udelay(1);
    memctl->memc_mcr  = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
    udelay(1);


    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

    udelay (1000);

    size_b0 = 0x00800000;
    size_b1 = 0x00800000;
    size_b2 = 0x00800000;


	memctl->memc_mptpr = CFG_MPTPR;
	udelay(1000);

	memctl->memc_or1 = 0xFF800A00;
	memctl->memc_br1 = 0x00000081;

    memctl->memc_or2 = 0xFF000A00;
    memctl->memc_br2 = 0x00800081;

	memctl->memc_or3 = 0xFE000A00;
	memctl->memc_br3 = 0x01000081;

    udelay(10000);


    return (size_b0 + size_b1 + size_b2);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */
#if 0
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
    volatile memctl8xx_t *memctl = &immap->im_memctl;
    volatile long int	 *addr;
    ulong		  cnt, val;
    ulong		  save[32];	/* to make test non-destructive */
    unsigned char	  i = 0;

    memctl->memc_mamr = mamr_value;

    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
	addr = base + cnt;	/* pointer arith! */

	save[i++] = *addr;
	*addr = ~cnt;
    }

    /* write 0 to base address */
    addr = base;
    save[i] = *addr;
    *addr = 0;

    /* check at base address */
    if ((val = *addr) != 0) {
	*addr = save[i];
	return (0);
    }

    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
	addr = base + cnt;	/* pointer arith! */

	val = *addr;
	*addr = save[--i];

	if (val != (~cnt)) {
	    return (cnt * sizeof(long));
	}
    }
    return (maxsize);
}
#endif

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_KUP4K_LOGO
	bd_t *bd = gd->bd;


	lcd_logo(bd);
#endif /* CONFIG_KUP4K_LOGO */
	return(0);
}

#ifdef CONFIG_KUP4K_LOGO
void lcd_logo(bd_t *bd){

    FB_INFO_S1D13xxx fb_info;
    S1D_INDEX s1dReg;
    S1D_VALUE s1dValue;
    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
    volatile	memctl8xx_t     *memctl;
	ushort i;
	uchar *fb;
    int rs, gs, bs;
    int r = 8, g = 8, b = 4;
    int r1,g1,b1;

/*----------------------------------------------------------------------------- */
/**/
/* Initialize the chip and the frame buffer driver. */
/**/
/*----------------------------------------------------------------------------- */
    memctl = &immr->im_memctl;
/*    memctl->memc_or5 = 0xFFC007F0;    / * 4 MB  17 WS or externel TA */
/*    memctl->memc_br5 = 0x80000801;    / * Start at 0x80000000 */

    memctl->memc_or5 = 0xFFC00708;    /* 4 MB  17 WS or externel TA */
    memctl->memc_br5 = 0x80080801;    /* Start at 0x80080000 */


    fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
    fb_info.RegAddr =  (unsigned char*)(S1D_PHYSICAL_REG_ADDR);

    if ((((S1D_VALUE*)fb_info.RegAddr)[0] != 0x28) || (((S1D_VALUE*)fb_info.RegAddr)[1] != 0x14))
    {
	  printf("Warning:LCD Controller S1D13706 not found\n");
	  return;
    }

    /* init controller */
    for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
    {
        s1dReg = aS1DRegs[i].Index;
        s1dValue = aS1DRegs[i].Value;
/*      printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
        ((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
    }

#undef MONOCHROME
#ifdef MONOCHROME
   	switch(bd->bi_busfreq){
#if 0
		case 24000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
			break;
		case 32000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
			break;
#endif
		case 40000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
			break;
		case 48000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
			break;
		default:
			printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
		case 64000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
			break;
	}
	((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
#else
	   	switch(bd->bi_busfreq){
#if 0
		case 24000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
			break;
		case 32000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
			break;
#endif
		case 40000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
			break;
		case 48000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
			break;
		default:
			printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
		case 64000000:
			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
			break;
	}
#endif

    
    /* create and set colormap */
    rs = 256 / (r - 1);
    gs = 256 / (g - 1);
    bs = 256 / (b - 1);
	for(i=0;i<256;i++){
       r1=(rs * ((i / (g * b)) % r)) * 255;
       g1=(gs * ((i / b) % g)) * 255;
       b1=(bs * ((i) % b)) * 255;
/*     printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
       S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
    }

    /* copy bitmap */
	fb   = (char *) (fb_info.VmemAddr);
	memcpy (fb, (uchar *)CONFIG_KUP4K_LOGO, 320 * 240);
}
#endif /* CONFIG_KUP4K_LOGO */
Commit	Line	Data
56f94be3 WD	1	/*
	2	* (C) Copyright 2000, 2001, 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <mpc8xx.h>
	27	#ifdef CONFIG_KUP4K_LOGO
	28	#include "s1d13706.h"
	29	#endif
	30
	31
	32	typedef struct
	33	{
	34	volatile unsigned char *VmemAddr;
	35	volatile unsigned char *RegAddr;
	36	}FB_INFO_S1D13xxx;
	37
	38	/* ------------------------------------------------------------------------- */
	39
	40	#if 0
	41	static long int dram_size (long int, long int *, long int);
	42	#endif
	43
	44	#ifdef CONFIG_KUP4K_LOGO
	45	void lcd_logo(bd_t *bd);
	46	#endif
	47
	48	/* ------------------------------------------------------------------------- */
	49
	50	#define _NOT_USED_ 0xFFFFFFFF
	51
	52	const uint sdram_table[] =
	53	{
	54	/*
	55	* Single Read. (Offset 0 in UPMA RAM)
	56	*/
	57	0x1F07FC04,
	58	0xEEAEFC04,
	59	0x11ADFC04,
	60	0xEFBBBC00,
	61	0x1FF77C47, /* last */
	62
	63	/*
	64	* SDRAM Initialization (offset 5 in UPMA RAM)
65	*
66	* This is no UPM entry point. The following definition uses
67	* the remaining space to establish an initialization
68	* sequence, which is executed by a RUN command.
69	*
70	*/
71	0x1FF77C35,
72	0xEFEABC34,
73	0x1FB57C35, /* last */
74
75	/*
76	* Burst Read. (Offset 8 in UPMA RAM)
77	*/
78	0x1F07FC04,
79	0xEEAEFC04,
80	0x10ADFC04,
81	0xF0AFFC00,
82	0xF0AFFC00,
83	0xF1AFFC00,
84	0xEFBBBC00,
85	0x1FF77C47, /* last */
86	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
87	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
88
89	/*
90	* Single Write. (Offset 18 in UPMA RAM)
91	*/
92	0x1F27FC04,
93	0xEEAEBC00,
94	0x01B93C04,
95	0x1FF77C47, /* last */
96	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
97
98	/*
99	* Burst Write. (Offset 20 in UPMA RAM)
100	*/
101	0x1F07FC04,
102	0xEEAEBC00,
103	0x10AD7C00,
104	0xF0AFFC00,
105	0xF0AFFC00,
106	0xE1BBBC04,
107	0x1FF77C47, /* last */
108	_NOT_USED_,
109	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
110	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
111
112	/*
113	* Refresh (Offset 30 in UPMA RAM)
114	*/
115	0x1FF5FC84,
116	0xFFFFFC04,
117	0xFFFFFC04,
118	0xFFFFFC04,
119	0xFFFFFC84,
120	0xFFFFFC07, /* last */
121	_NOT_USED_, _NOT_USED_,
122	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
123
124	/*
125	* Exception. (Offset 3c in UPMA RAM)
126	*/
127	0x7FFFFC07, /* last */
128	_NOT_USED_, _NOT_USED_, _NOT_USED_,
129	};
130
131	/* ------------------------------------------------------------------------- */
132
133
134	/*
135	* Check Board Identity:
136	*/
137
138	int checkboard (void)
139	{
140
141	printf ("### No HW ID - assuming KUP4K-Color\n");
142	return (0);
143	}
144
145	/* ------------------------------------------------------------------------- */
146
147	long int initdram (int board_type)
148	{
149	volatile immap_t immap = (immap_t )CFG_IMMR;
150	volatile memctl8xx_t *memctl = &immap->im_memctl;
151	long int size_b0 = 0;
152	long int size_b1 = 0;
153	long int size_b2 = 0;
154
155	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
156
157	/*
158	* Preliminary prescaler for refresh (depends on number of
159	* banks): This value is selected for four cycles every 62.4 us
160	* with two SDRAM banks or four cycles every 31.2 us with one
161	* bank. It will be adjusted after memory sizing.
162	*/
163	memctl->memc_mptpr = CFG_MPTPR;
164
165	memctl->memc_mar = 0x00000088;
166
167	/*
168	* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
169	* preliminary addresses - these have to be modified after the
170	* SDRAM size has been determined.
171	*/
172	/* memctl->memc_or1 = CFG_OR1_PRELIM; */
173	/* memctl->memc_br1 = CFG_BR1_PRELIM; */
174
175	/* memctl->memc_or2 = CFG_OR2_PRELIM; */
176	/* memctl->memc_br2 = CFG_BR2_PRELIM; */
177
178
179	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
180
181	udelay(200);
182
183	/* perform SDRAM initializsation sequence */
184
185	memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
186	udelay(1);
187	memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
188	udelay(1);
189	memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
190	udelay(1);
191
192	memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
193	udelay(1);
194	memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
195	udelay(1);
196	memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
197	udelay(1);
198
199	memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
200	udelay(1);
201	memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
202	udelay(1);
203	memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
204	udelay(1);
205
206
207	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
208
209	udelay (1000);
210
211	size_b0 = 0x00800000;
212	size_b1 = 0x00800000;
213	size_b2 = 0x00800000;
214
215
216	memctl->memc_mptpr = CFG_MPTPR;
217	udelay(1000);
218
219	memctl->memc_or1 = 0xFF800A00;
220	memctl->memc_br1 = 0x00000081;
221
222	memctl->memc_or2 = 0xFF000A00;
223	memctl->memc_br2 = 0x00800081;
224
225	memctl->memc_or3 = 0xFE000A00;
226	memctl->memc_br3 = 0x01000081;
227
228	udelay(10000);
229
230
231	return (size_b0 + size_b1 + size_b2);
232	}
233
234	/* ------------------------------------------------------------------------- */
235
236	/*
237	* Check memory range for valid RAM. A simple memory test determines
238	* the actually available RAM size between addresses `base' and
239	* `base + maxsize'. Some (not all) hardware errors are detected:
240	* - short between address lines
241	* - short between data lines
242	*/
243	#if 0
244	static long int dram_size (long int mamr_value, long int *base, long int maxsize)
245	{
246	volatile immap_t immap = (immap_t )CFG_IMMR;
247	volatile memctl8xx_t *memctl = &immap->im_memctl;
248	volatile long int *addr;
249	ulong cnt, val;
250	ulong save[32]; /* to make test non-destructive */
251	unsigned char i = 0;
252
253	memctl->memc_mamr = mamr_value;
254
255	for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
256	addr = base + cnt; /* pointer arith! */
257
258	save[i++] = *addr;
259	*addr = ~cnt;
260	}
261
262	/* write 0 to base address */
263	addr = base;
264	save[i] = *addr;
265	*addr = 0;
266
267	/* check at base address */
268	if ((val = *addr) != 0) {
269	*addr = save[i];
270	return (0);
271	}
272
273	for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
274	addr = base + cnt; /* pointer arith! */
275
276	val = *addr;
277	*addr = save[--i];
278
279	if (val != (~cnt)) {
280	return (cnt * sizeof(long));
281	}
282	}
283	return (maxsize);
284	}
285	#endif
286
287	int misc_init_r (void)
288	{
289	DECLARE_GLOBAL_DATA_PTR;
290
291	#ifdef CONFIG_KUP4K_LOGO
292	bd_t *bd = gd->bd;
293
294
295	lcd_logo(bd);
296	#endif /* CONFIG_KUP4K_LOGO */
297	return(0);
298	}
299
300	#ifdef CONFIG_KUP4K_LOGO
301	void lcd_logo(bd_t *bd){
302
303	FB_INFO_S1D13xxx fb_info;
304	S1D_INDEX s1dReg;
305	S1D_VALUE s1dValue;
306	volatile immap_t immr = (immap_t )CFG_IMMR;
307	volatile memctl8xx_t *memctl;
308	ushort i;
309	uchar *fb;
310	int rs, gs, bs;
311	int r = 8, g = 8, b = 4;
312	int r1,g1,b1;
313
314	/----------------------------------------------------------------------------- /
315	/**/
316	/* Initialize the chip and the frame buffer driver. */
317	/**/
318	/----------------------------------------------------------------------------- /
319	memctl = &immr->im_memctl;
320	/* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */
321	/* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */
322
323	memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
324	memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
325
326
327
328
329
330	fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
331	fb_info.RegAddr = (unsigned char*)(S1D_PHYSICAL_REG_ADDR);
332
333	if ((((S1D_VALUE)fb_info.RegAddr)[0] != 0x28) \|\| (((S1D_VALUE)fb_info.RegAddr)[1] != 0x14))
334	{
335	printf("Warning:LCD Controller S1D13706 not found\n");
336	return;
337	}
338
339	/* init controller */
340	for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
341	{
342	s1dReg = aS1DRegs[i].Index;
343	s1dValue = aS1DRegs[i].Value;
344	/* printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
345	((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
346	}
347
348	#undef MONOCHROME
349	#ifdef MONOCHROME
350	switch(bd->bi_busfreq){
351	#if 0
352	case 24000000:
353	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
354	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
355	break;
356	case 32000000:
357	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
358	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
359	break;
360	#endif
361	case 40000000:
362	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
363	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
364	break;
365	case 48000000:
366	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
367	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
368	break;
369	default:
370	printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
371	case 64000000:
372	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
373	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
374	break;
375	}
376	((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
377	#else
378	switch(bd->bi_busfreq){
379	#if 0
380	case 24000000:
381	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
382	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
383	break;
384	case 32000000:
385	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
386	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
387	break;
388	#endif
389	case 40000000:
390	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
391	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
392	break;
393	case 48000000:
394	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
395	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
396	break;
397	default:
398	printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
399	case 64000000:
400	((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
401	((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
402	break;
403	}
404	#endif
405
406
407	/* create and set colormap */
408	rs = 256 / (r - 1);
409	gs = 256 / (g - 1);
410	bs = 256 / (b - 1);
411	for(i=0;i<256;i++){
412	r1=(rs * ((i / (g * b)) % r)) * 255;
413	g1=(gs * ((i / b) % g)) * 255;
414	b1=(bs * ((i) % b)) * 255;
415	/* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
416	S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
417	}
418
419	/* copy bitmap */
420	fb = (char *) (fb_info.VmemAddr);
421	memcpy (fb, (uchar )CONFIG_KUP4K_LOGO, 320 240);
422	}
423	#endif /* CONFIG_KUP4K_LOGO */
424