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Commit | Line | Data |
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d9fd6ff5 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
d9fd6ff5 WD |
10 | */ |
11 | ||
12 | #include <common.h> | |
1ab70f6f | 13 | #include <netdev.h> |
4438a45f | 14 | #include <asm/arch/pxa.h> |
e570fe8e | 15 | #include <asm/arch/pxa-regs.h> |
831f849f | 16 | #include <asm/arch/regs-mmc.h> |
e570fe8e | 17 | #include <asm/io.h> |
d9fd6ff5 | 18 | |
d87080b7 | 19 | DECLARE_GLOBAL_DATA_PTR; |
d9fd6ff5 WD |
20 | |
21 | /* | |
22 | * Miscelaneous platform dependent initialisations | |
23 | */ | |
24 | ||
25 | int board_init (void) | |
26 | { | |
3c43ca2a MV |
27 | /* We have RAM, disable cache */ |
28 | dcache_disable(); | |
29 | icache_disable(); | |
d9fd6ff5 WD |
30 | |
31 | /* arch number of Lubbock-Board */ | |
731215eb | 32 | gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; |
d9fd6ff5 WD |
33 | |
34 | /* adress of boot parameters */ | |
35 | gd->bd->bi_boot_params = 0xa0000100; | |
36 | ||
e570fe8e MV |
37 | /* Configure GPIO6 and GPIO8 as OUT, AF1. */ |
38 | setbits_le32(GPDR0, (1 << 6) | (1 << 8)); | |
39 | clrsetbits_le32(GAFR0_L, (3 << 12) | (3 << 16), (1 << 12) | (1 << 16)); | |
40 | ||
db2f721f | 41 | return 0; |
d9fd6ff5 WD |
42 | } |
43 | ||
831f849f MV |
44 | #ifdef CONFIG_CMD_MMC |
45 | int board_mmc_init(bd_t *bis) | |
46 | { | |
47 | pxa_mmc_register(0); | |
48 | return 0; | |
49 | } | |
50 | #endif | |
51 | ||
c837dcb1 | 52 | int board_late_init(void) |
71f95118 | 53 | { |
c837dcb1 WD |
54 | setenv("stdout", "serial"); |
55 | setenv("stderr", "serial"); | |
71f95118 WD |
56 | return 0; |
57 | } | |
58 | ||
3c43ca2a MV |
59 | int dram_init(void) |
60 | { | |
f68d2a22 | 61 | pxa2xx_dram_init(); |
3c43ca2a MV |
62 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
63 | return 0; | |
64 | } | |
71f95118 | 65 | |
3c43ca2a | 66 | void dram_init_banksize(void) |
d9fd6ff5 | 67 | { |
d9fd6ff5 WD |
68 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
69 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
d9fd6ff5 | 70 | } |
1ab70f6f BW |
71 | |
72 | #ifdef CONFIG_CMD_NET | |
73 | int board_eth_init(bd_t *bis) | |
74 | { | |
75 | int rc = 0; | |
76 | #ifdef CONFIG_LAN91C96 | |
77 | rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); | |
78 | #endif | |
79 | return rc; | |
80 | } | |
81 | #endif |