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1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
25ddd1fb | 26 | #include <asm-offsets.h> |
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27 | #include <ppc_asm.tmpl> |
28 | #include <config.h> | |
61f2b38a | 29 | #include <asm/mmu.h> |
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30 | |
31 | /************************************************************************** | |
32 | * TLB TABLE | |
33 | * | |
34 | * This table is used by the cpu boot code to setup the initial tlb | |
35 | * entries. Rather than make broad assumptions in the cpu source tree, | |
36 | * this table lets each board set things up however they like. | |
37 | * | |
38 | * Pointer to the table is returned in r1 | |
39 | * | |
40 | *************************************************************************/ | |
41 | .section .bootpg,"ax" | |
42 | .globl tlbtab | |
43 | ||
44 | tlbtab: | |
45 | tlbtab_start | |
46 | ||
47 | /* | |
48 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
49 | * speed up boot process. It is patched after relocation to enable SA_I | |
50 | */ | |
cf6eb6da | 51 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G) |
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52 | |
53 | /* | |
54 | * TLB entries for SDRAM are not needed on this platform. | |
55 | * They are dynamically generated in the SPD DDR(2) detection | |
56 | * routine. | |
57 | */ | |
58 | ||
6d0f6bcf | 59 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
b765ffb7 | 60 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
cf6eb6da | 61 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) |
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62 | #endif |
63 | ||
64 | /* TLB-entry for PCI Memory */ | |
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65 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG) |
66 | tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG) | |
67 | tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG) | |
68 | tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG) | |
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69 | |
70 | /* TLB-entry for the FPGA Chip select 2 */ | |
cf6eb6da | 71 | tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G) |
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72 | |
73 | /* TLB-entry for the FPGA Chip select 3 */ | |
cf6eb6da | 74 | tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G) |
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75 | |
76 | /* TLB-entry for the LIME Controller */ | |
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77 | tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G) |
78 | tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G) | |
79 | tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G) | |
80 | tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G) | |
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81 | |
82 | /* TLB-entry for Internal Registers & OCM */ | |
cf6eb6da | 83 | tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I) |
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84 | |
85 | /*TLB-entry PCI registers*/ | |
cf6eb6da | 86 | tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG) |
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87 | |
88 | /* TLB-entry for peripherals */ | |
cf6eb6da | 89 | tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) |
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90 | |
91 | tlbtab_end |