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Commit | Line | Data |
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b765ffb7 | 1 | /* |
f47b048b | 2 | * (C) Copyright 2007-2013 |
b765ffb7 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
b765ffb7 SR |
6 | */ |
7 | ||
8 | #include <common.h> | |
c25dd8fc | 9 | #include <command.h> |
b36df561 | 10 | #include <asm/ppc440.h> |
04e6c38b | 11 | #include <asm/processor.h> |
09887762 | 12 | #include <asm/ppc4xx-gpio.h> |
04e6c38b | 13 | #include <asm/io.h> |
f14ae418 SL |
14 | #include <post.h> |
15 | #include <flash.h> | |
16 | #include <mtd/cfi_flash.h> | |
b765ffb7 SR |
17 | |
18 | DECLARE_GLOBAL_DATA_PTR; | |
19 | ||
f14ae418 | 20 | static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST; |
b765ffb7 | 21 | |
3ad63878 SR |
22 | ulong flash_get_size(ulong base, int banknum); |
23 | int misc_init_r_kbd(void); | |
b765ffb7 SR |
24 | |
25 | int board_early_init_f(void) | |
26 | { | |
27 | u32 sdr0_pfc1, sdr0_pfc2; | |
28 | u32 reg; | |
29 | ||
83b4cfa3 | 30 | /* PLB Write pipelining disabled. Denali Core workaround */ |
5e7abce9 SR |
31 | mtdcr(PLB4A0_ACR, 0xDE000000); |
32 | mtdcr(PLB4A1_ACR, 0xDE000000); | |
b765ffb7 SR |
33 | |
34 | /*-------------------------------------------------------------------- | |
35 | * Setup the interrupt controller polarities, triggers, etc. | |
36 | *-------------------------------------------------------------------*/ | |
952e7760 SR |
37 | mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ |
38 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
39 | mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ | |
40 | mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ | |
41 | mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ | |
42 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ | |
43 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ | |
b765ffb7 | 44 | |
952e7760 SR |
45 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
46 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
47 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ | |
48 | mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ | |
49 | mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ | |
50 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ | |
51 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
b765ffb7 | 52 | |
952e7760 SR |
53 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
54 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
55 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
56 | mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ | |
57 | mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ | |
58 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ | |
59 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
b765ffb7 SR |
60 | |
61 | /* Trace Pins are disabled. SDR0_PFC0 Register */ | |
62 | mtsdr(SDR0_PFC0, 0x0); | |
63 | ||
64 | /* select Ethernet pins */ | |
65 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
66 | /* SMII via ZMII */ | |
67 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | | |
68 | SDR0_PFC1_SELECT_CONFIG_6; | |
69 | mfsdr(SDR0_PFC2, sdr0_pfc2); | |
70 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | | |
71 | SDR0_PFC2_SELECT_CONFIG_6; | |
72 | ||
73 | /* enable SPI (SCP) */ | |
74 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; | |
75 | ||
76 | mtsdr(SDR0_PFC2, sdr0_pfc2); | |
77 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
78 | ||
79 | mtsdr(SDR0_PFC4, 0x80000000); | |
80 | ||
81 | /* PCI arbiter disabled */ | |
83b4cfa3 | 82 | /* PCI Host Configuration disbaled */ |
d1c3b275 | 83 | mfsdr(SDR0_PCI0, reg); |
83b4cfa3 | 84 | reg = 0; |
d1c3b275 | 85 | mtsdr(SDR0_PCI0, 0x00000000 | reg); |
b765ffb7 | 86 | |
6d0f6bcf | 87 | gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); |
b765ffb7 | 88 | |
6d0f6bcf | 89 | #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 |
f14ae418 SL |
90 | /* enable the LSB transmitter */ |
91 | gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); | |
92 | /* enable the CAN transmitter */ | |
93 | gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); | |
65b20dce YT |
94 | |
95 | reg = 0; /* reuse as counter */ | |
6d0f6bcf JCPV |
96 | out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, |
97 | in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | |
98 | & ~CONFIG_SYS_DSPIC_TEST_MASK); | |
f14ae418 | 99 | while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { |
65b20dce YT |
100 | udelay(1000); |
101 | } | |
6d0f6bcf | 102 | if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { |
65b20dce | 103 | /* set "boot error" flag */ |
6d0f6bcf JCPV |
104 | out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, |
105 | in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | | |
106 | CONFIG_SYS_DSPIC_TEST_MASK); | |
65b20dce YT |
107 | } |
108 | #endif | |
109 | ||
54fd6c93 SR |
110 | /* |
111 | * Reset PHY's: | |
112 | * The PHY's need a 2nd reset pulse, since the MDIO address is latched | |
113 | * upon reset, and with the first reset upon powerup, the addresses are | |
114 | * not latched reliable, since the IRQ line is multiplexed with an | |
115 | * MDIO address. A 2nd reset at this time will make sure, that the | |
116 | * correct address is latched. | |
117 | */ | |
6d0f6bcf JCPV |
118 | gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); |
119 | gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); | |
54fd6c93 | 120 | udelay(1000); |
6d0f6bcf JCPV |
121 | gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); |
122 | gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); | |
54fd6c93 | 123 | udelay(1000); |
6d0f6bcf JCPV |
124 | gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); |
125 | gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); | |
54fd6c93 | 126 | |
b765ffb7 SR |
127 | return 0; |
128 | } | |
129 | ||
f14ae418 SL |
130 | /* |
131 | * Override weak default with board specific version | |
132 | */ | |
133 | phys_addr_t cfi_flash_bank_addr(int bank) | |
134 | { | |
135 | return lwmon5_cfi_flash_bank_addr[bank]; | |
136 | } | |
137 | ||
138 | /* | |
139 | * Override the weak default mapping function with a board specific one | |
140 | */ | |
141 | u32 flash_get_bank_size(int cs, int idx) | |
142 | { | |
143 | return flash_info[idx].size; | |
144 | } | |
145 | ||
146 | int board_early_init_r(void) | |
147 | { | |
148 | u32 val0, val1; | |
149 | ||
150 | /* | |
151 | * lwmon5 is manufactured in 2 different board versions: | |
152 | * The lwmon5a board has 64MiB NOR flash instead of the | |
153 | * 128MiB of the original lwmon5. Unfortunately the CFI driver | |
154 | * will report 2 banks of 64MiB even for the smaller flash | |
155 | * chip, since the bank is mirrored. To fix this, we bring | |
156 | * one bank into CFI query mode and read its response. This | |
157 | * enables us to detect the real number of flash devices/ | |
158 | * banks which will be used later on by the common CFI driver. | |
159 | */ | |
160 | ||
161 | /* Put bank 0 into CFI command mode and read */ | |
162 | out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098); | |
163 | val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP); | |
164 | val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP); | |
165 | ||
166 | /* Reset flash again out of query mode */ | |
167 | out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0); | |
168 | ||
169 | /* When not identical, we have 2 different flash devices/banks */ | |
170 | if (val0 != val1) | |
171 | return 0; | |
172 | ||
173 | /* | |
174 | * Now we're sure that we're running on a LWMON5a board with | |
175 | * only 64MiB NOR flash in one bank: | |
176 | * | |
177 | * Set flash base address and bank count for CFI driver probing. | |
178 | */ | |
179 | cfi_flash_num_flash_banks = 1; | |
180 | lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
b765ffb7 SR |
185 | int misc_init_r(void) |
186 | { | |
187 | u32 pbcr; | |
188 | int size_val = 0; | |
189 | u32 reg; | |
f47b048b | 190 | #ifndef CONFIG_LCD4_LWMON5 |
b765ffb7 SR |
191 | unsigned long usb2d0cr = 0; |
192 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
f14ae418 | 193 | unsigned long sdr0_pfc1, sdr0_srst; |
f47b048b | 194 | #endif |
b765ffb7 SR |
195 | |
196 | /* | |
197 | * FLASH stuff... | |
198 | */ | |
199 | ||
200 | /* Re-do sizing to get full correct info */ | |
201 | ||
202 | /* adjust flash start and offset */ | |
203 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
204 | gd->bd->bi_flashoffset = 0; | |
205 | ||
d1c3b275 | 206 | mfebc(PB0CR, pbcr); |
f14ae418 | 207 | size_val = ffs(gd->bd->bi_flashsize) - 21; |
b765ffb7 | 208 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
d1c3b275 | 209 | mtebc(PB0CR, pbcr); |
b765ffb7 SR |
210 | |
211 | /* | |
212 | * Re-check to get correct base address | |
213 | */ | |
214 | flash_get_size(gd->bd->bi_flashstart, 0); | |
215 | ||
216 | /* Monitor protection ON by default */ | |
f14ae418 SL |
217 | flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, |
218 | &flash_info[cfi_flash_num_flash_banks - 1]); | |
b765ffb7 SR |
219 | |
220 | /* Env protection ON by default */ | |
f14ae418 SL |
221 | flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, |
222 | CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, | |
223 | &flash_info[cfi_flash_num_flash_banks - 1]); | |
b765ffb7 | 224 | |
f47b048b | 225 | #ifndef CONFIG_LCD4_LWMON5 |
b765ffb7 SR |
226 | /* |
227 | * USB suff... | |
228 | */ | |
f14ae418 SL |
229 | |
230 | /* Reset USB */ | |
231 | /* Reset of USB2PHY0 must be active at least 10 us */ | |
232 | mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D); | |
233 | udelay(2000); | |
234 | ||
235 | mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI | | |
236 | SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 | | |
237 | SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40); | |
238 | udelay(2000); | |
239 | ||
240 | /* Errata CHIP_6 */ | |
241 | ||
242 | /* 1. Set internal PHY configuration */ | |
b765ffb7 SR |
243 | /* SDR Setting */ |
244 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
245 | mfsdr(SDR0_USB0, usb2d0cr); | |
246 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
247 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
248 | ||
f14ae418 SL |
249 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; |
250 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
251 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; | |
252 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ | |
253 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; | |
254 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ | |
255 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
256 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ | |
257 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; | |
258 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ | |
259 | ||
260 | /* | |
261 | * An 8-bit/60MHz interface is the only possible alternative | |
262 | * when connecting the Device to the PHY | |
263 | */ | |
264 | usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; | |
265 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ | |
b765ffb7 SR |
266 | |
267 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
268 | mtsdr(SDR0_USB0, usb2d0cr); | |
269 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
270 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
271 | ||
f14ae418 SL |
272 | /* 2. De-assert internal PHY reset */ |
273 | mfsdr(SDR0_SRST1, sdr0_srst); | |
274 | sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY; | |
275 | mtsdr(SDR0_SRST1, sdr0_srst); | |
276 | ||
277 | /* 3. Wait for more than 1 ms */ | |
278 | udelay(2000); | |
279 | ||
280 | /* 4. De-assert USB 2.0 Host main reset */ | |
281 | mfsdr(SDR0_SRST0, sdr0_srst); | |
282 | sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H; | |
283 | mtsdr(SDR0_SRST0, sdr0_srst); | |
284 | udelay(1000); | |
285 | ||
286 | /* 5. De-assert reset of OPB2 cores */ | |
287 | mfsdr(SDR0_SRST1, sdr0_srst); | |
288 | sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1; | |
289 | sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40; | |
290 | sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2; | |
291 | mtsdr(SDR0_SRST1, sdr0_srst); | |
292 | udelay(1000); | |
293 | ||
294 | /* 6. Set EHCI Configure FLAG */ | |
295 | ||
296 | /* 7. Reassert internal PHY reset: */ | |
297 | mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); | |
298 | udelay(1000); | |
f47b048b | 299 | #endif |
f14ae418 | 300 | |
b765ffb7 SR |
301 | /* |
302 | * Clear resets | |
303 | */ | |
b765ffb7 | 304 | mtsdr(SDR0_SRST1, 0x00000000); |
b765ffb7 SR |
305 | mtsdr(SDR0_SRST0, 0x00000000); |
306 | ||
f47b048b | 307 | #ifndef CONFIG_LCD4_LWMON5 |
b765ffb7 | 308 | printf("USB: Host(int phy) Device(ext phy)\n"); |
f47b048b | 309 | #endif |
b765ffb7 SR |
310 | |
311 | /* | |
312 | * Clear PLB4A0_ACR[WRP] | |
313 | * This fix will make the MAL burst disabling patch for the Linux | |
314 | * EMAC driver obsolete. | |
315 | */ | |
5e7abce9 SR |
316 | reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; |
317 | mtdcr(PLB4A0_ACR, reg); | |
b765ffb7 | 318 | |
f47b048b | 319 | #ifndef CONFIG_LCD4_LWMON5 |
3ad63878 SR |
320 | /* |
321 | * Init matrix keyboard | |
322 | */ | |
323 | misc_init_r_kbd(); | |
f47b048b | 324 | #endif |
3ad63878 | 325 | |
b765ffb7 SR |
326 | return 0; |
327 | } | |
328 | ||
329 | int checkboard(void) | |
330 | { | |
f0c0b3a9 WD |
331 | char buf[64]; |
332 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
b765ffb7 | 333 | |
f47b048b | 334 | printf("Board: %s", __stringify(CONFIG_HOSTNAME)); |
b765ffb7 | 335 | |
f0c0b3a9 | 336 | if (i > 0) { |
b765ffb7 | 337 | puts(", serial# "); |
f0c0b3a9 | 338 | puts(buf); |
b765ffb7 SR |
339 | } |
340 | putc('\n'); | |
341 | ||
342 | return (0); | |
343 | } | |
344 | ||
b765ffb7 SR |
345 | void hw_watchdog_reset(void) |
346 | { | |
347 | int val; | |
d32a874b YT |
348 | #if defined(CONFIG_WD_MAX_RATE) |
349 | unsigned long long ct = get_ticks(); | |
350 | ||
351 | /* | |
352 | * Don't allow watch-dog triggering more frequently than | |
353 | * the predefined value CONFIG_WD_MAX_RATE [ticks]. | |
354 | */ | |
a0d3c820 SG |
355 | if (ct >= gd->arch.wdt_last) { |
356 | if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE) | |
d32a874b YT |
357 | return; |
358 | } else { | |
359 | /* Time base counter had been reset */ | |
a0d3c820 | 360 | if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) < |
d32a874b YT |
361 | CONFIG_WD_MAX_RATE) |
362 | return; | |
363 | } | |
a0d3c820 | 364 | gd->arch.wdt_last = get_ticks(); |
d32a874b | 365 | #endif |
b765ffb7 SR |
366 | |
367 | /* | |
368 | * Toggle watchdog output | |
369 | */ | |
6d0f6bcf JCPV |
370 | val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0; |
371 | gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val); | |
b765ffb7 | 372 | } |
c25dd8fc | 373 | |
54841ab5 | 374 | int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
c25dd8fc | 375 | { |
47e26b1b WD |
376 | if (argc < 2) |
377 | return cmd_usage(cmdtp); | |
c25dd8fc | 378 | |
47e26b1b | 379 | if ((strcmp(argv[1], "on") == 0)) |
6d0f6bcf | 380 | gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1); |
47e26b1b | 381 | else if ((strcmp(argv[1], "off") == 0)) |
6d0f6bcf | 382 | gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0); |
47e26b1b WD |
383 | else |
384 | return cmd_usage(cmdtp); | |
c25dd8fc SR |
385 | |
386 | return 0; | |
387 | } | |
388 | ||
389 | U_BOOT_CMD( | |
390 | eepromwp, 2, 0, do_eeprom_wp, | |
2fb2604d | 391 | "eeprom write protect off/on", |
a89c33db | 392 | "<on|off> - enable (on) or disable (off) I2C EEPROM write protect" |
c25dd8fc | 393 | ); |
d610a607 AG |
394 | |
395 | #if defined(CONFIG_VIDEO) | |
396 | #include <video_fb.h> | |
397 | #include <mb862xx.h> | |
398 | ||
399 | extern GraphicDevice mb862xx; | |
400 | ||
f14ae418 SL |
401 | static const gdc_regs init_regs [] = { |
402 | { 0x0100, 0x00000f00 }, | |
403 | { 0x0020, 0x801401df }, | |
404 | { 0x0024, 0x00000000 }, | |
405 | { 0x0028, 0x00000000 }, | |
406 | { 0x002c, 0x00000000 }, | |
407 | { 0x0110, 0x00000000 }, | |
408 | { 0x0114, 0x00000000 }, | |
409 | { 0x0118, 0x01df0280 }, | |
410 | { 0x0004, 0x031f0000 }, | |
411 | { 0x0008, 0x027f027f }, | |
412 | { 0x000c, 0x015f028f }, | |
413 | { 0x0010, 0x020c0000 }, | |
414 | { 0x0014, 0x01df01ea }, | |
415 | { 0x0018, 0x00000000 }, | |
416 | { 0x001c, 0x01e00280 }, | |
417 | { 0x0100, 0x80010f00 }, | |
418 | { 0x0, 0x0 } | |
d610a607 AG |
419 | }; |
420 | ||
f14ae418 | 421 | const gdc_regs *board_get_regs(void) |
d610a607 AG |
422 | { |
423 | return init_regs; | |
424 | } | |
425 | ||
426 | /* Returns Lime base address */ | |
f14ae418 | 427 | unsigned int board_video_init(void) |
d610a607 AG |
428 | { |
429 | /* | |
430 | * Reset Lime controller | |
431 | */ | |
6d0f6bcf | 432 | gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); |
d610a607 | 433 | udelay(500); |
6d0f6bcf | 434 | gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); |
d610a607 | 435 | |
d610a607 AG |
436 | mb862xx.winSizeX = 640; |
437 | mb862xx.winSizeY = 480; | |
438 | mb862xx.gdfBytesPP = 2; | |
439 | mb862xx.gdfIndex = GDF_15BIT_555RGB; | |
440 | ||
6d0f6bcf | 441 | return CONFIG_SYS_LIME_BASE_0; |
d610a607 AG |
442 | } |
443 | ||
f14ae418 | 444 | #define DEFAULT_BRIGHTNESS 0x64 |
0f855a1f YT |
445 | |
446 | static void board_backlight_brightness(int brightness) | |
d610a607 | 447 | { |
0f855a1f | 448 | if (brightness > 0) { |
d610a607 | 449 | /* pwm duty, lamp on */ |
6d0f6bcf JCPV |
450 | out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness); |
451 | out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701); | |
d610a607 AG |
452 | } else { |
453 | /* lamp off */ | |
6d0f6bcf JCPV |
454 | out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00); |
455 | out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00); | |
d610a607 AG |
456 | } |
457 | } | |
458 | ||
f14ae418 | 459 | void board_backlight_switch(int flag) |
0f855a1f YT |
460 | { |
461 | char * param; | |
462 | int rc; | |
463 | ||
464 | if (flag) { | |
465 | param = getenv("brightness"); | |
466 | rc = param ? simple_strtol(param, NULL, 10) : -1; | |
467 | if (rc < 0) | |
468 | rc = DEFAULT_BRIGHTNESS; | |
469 | } else { | |
470 | rc = 0; | |
471 | } | |
472 | board_backlight_brightness(rc); | |
473 | } | |
474 | ||
d610a607 AG |
475 | #if defined(CONFIG_CONSOLE_EXTRA_INFO) |
476 | /* | |
477 | * Return text to be printed besides the logo. | |
478 | */ | |
f14ae418 | 479 | void video_get_info_str(int line_number, char *info) |
d610a607 | 480 | { |
f14ae418 SL |
481 | if (line_number == 1) |
482 | strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); | |
483 | else | |
d610a607 | 484 | info [0] = '\0'; |
d610a607 | 485 | } |
f14ae418 | 486 | #endif /* CONFIG_CONSOLE_EXTRA_INFO */ |
d610a607 | 487 | #endif /* CONFIG_VIDEO */ |
ff818b21 YT |
488 | |
489 | void board_reset(void) | |
490 | { | |
6d0f6bcf | 491 | gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1); |
ff818b21 | 492 | } |
f47b048b SR |
493 | |
494 | #ifdef CONFIG_SPL_OS_BOOT | |
495 | /* | |
496 | * lwmon5 specific implementation of spl_start_uboot() | |
497 | * | |
498 | * RETURN | |
499 | * 0 if booting into OS is selected (default) | |
500 | * 1 if booting into U-Boot is selected | |
501 | */ | |
502 | int spl_start_uboot(void) | |
503 | { | |
504 | char s[8]; | |
505 | ||
506 | env_init(); | |
507 | getenv_f("boot_os", s, sizeof(s)); | |
508 | if ((s != NULL) && (strcmp(s, "yes") == 0)) | |
509 | return 0; | |
510 | ||
511 | return 1; | |
512 | } | |
513 | ||
514 | /* | |
515 | * This function is called from the SPL U-Boot version for | |
516 | * early init stuff, that needs to be done for OS (e.g. Linux) | |
517 | * booting. Doing it later in the real U-Boot would not work | |
518 | * in case that the SPL U-Boot boots Linux directly. | |
519 | */ | |
520 | void spl_board_init(void) | |
521 | { | |
522 | const gdc_regs *regs = board_get_regs(); | |
523 | ||
524 | /* | |
525 | * Setup PFC registers, mainly for ethernet support | |
526 | * later on in Linux | |
527 | */ | |
528 | board_early_init_f(); | |
529 | ||
9055f66c SR |
530 | /* enable the LSB transmitter */ |
531 | gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); | |
532 | ||
f47b048b SR |
533 | /* |
534 | * Clear resets | |
535 | */ | |
536 | mtsdr(SDR0_SRST1, 0x00000000); | |
537 | mtsdr(SDR0_SRST0, 0x00000000); | |
538 | ||
539 | /* | |
540 | * Reset Lime controller | |
541 | */ | |
542 | gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); | |
543 | udelay(500); | |
544 | gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); | |
545 | ||
546 | out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF); | |
547 | udelay(300); | |
548 | out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR); | |
549 | ||
550 | while (regs->index) { | |
551 | out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) + | |
552 | regs->index, regs->value); | |
553 | regs++; | |
554 | } | |
555 | ||
556 | board_backlight_brightness(DEFAULT_BRIGHTNESS); | |
557 | } | |
558 | #endif |