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b765ffb7 SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <common.h> | |
c25dd8fc | 22 | #include <command.h> |
b765ffb7 | 23 | #include <ppc440.h> |
04e6c38b | 24 | #include <asm/processor.h> |
b765ffb7 | 25 | #include <asm/gpio.h> |
04e6c38b | 26 | #include <asm/io.h> |
b765ffb7 SR |
27 | |
28 | DECLARE_GLOBAL_DATA_PTR; | |
29 | ||
30 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
31 | ||
3ad63878 SR |
32 | ulong flash_get_size(ulong base, int banknum); |
33 | int misc_init_r_kbd(void); | |
b765ffb7 SR |
34 | |
35 | int board_early_init_f(void) | |
36 | { | |
37 | u32 sdr0_pfc1, sdr0_pfc2; | |
38 | u32 reg; | |
39 | ||
83b4cfa3 WD |
40 | /* PLB Write pipelining disabled. Denali Core workaround */ |
41 | mtdcr(plb0_acr, 0xDE000000); | |
42 | mtdcr(plb1_acr, 0xDE000000); | |
b765ffb7 SR |
43 | |
44 | /*-------------------------------------------------------------------- | |
45 | * Setup the interrupt controller polarities, triggers, etc. | |
46 | *-------------------------------------------------------------------*/ | |
47 | mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ | |
48 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
49 | mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ | |
aedf5bde SR |
50 | mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */ |
51 | mtdcr(uic0tr, 0x00000900); /* per ref-board manual */ | |
b765ffb7 SR |
52 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
53 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
54 | ||
55 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
56 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
57 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
aedf5bde SR |
58 | mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */ |
59 | mtdcr(uic1tr, 0x60000040); /* per ref-board manual */ | |
b765ffb7 SR |
60 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
61 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
62 | ||
63 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
64 | mtdcr(uic2er, 0x00000000); /* disable all */ | |
65 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ | |
66 | mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ | |
aedf5bde | 67 | mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */ |
b765ffb7 | 68 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ |
aedf5bde | 69 | mtdcr(uic2sr, 0xffffffff); /* clear all */ |
b765ffb7 SR |
70 | |
71 | /* Trace Pins are disabled. SDR0_PFC0 Register */ | |
72 | mtsdr(SDR0_PFC0, 0x0); | |
73 | ||
74 | /* select Ethernet pins */ | |
75 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
76 | /* SMII via ZMII */ | |
77 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | | |
78 | SDR0_PFC1_SELECT_CONFIG_6; | |
79 | mfsdr(SDR0_PFC2, sdr0_pfc2); | |
80 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | | |
81 | SDR0_PFC2_SELECT_CONFIG_6; | |
82 | ||
83 | /* enable SPI (SCP) */ | |
84 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; | |
85 | ||
86 | mtsdr(SDR0_PFC2, sdr0_pfc2); | |
87 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
88 | ||
89 | mtsdr(SDR0_PFC4, 0x80000000); | |
90 | ||
91 | /* PCI arbiter disabled */ | |
83b4cfa3 | 92 | /* PCI Host Configuration disbaled */ |
b765ffb7 | 93 | mfsdr(sdr_pci0, reg); |
83b4cfa3 | 94 | reg = 0; |
b765ffb7 SR |
95 | mtsdr(sdr_pci0, 0x00000000 | reg); |
96 | ||
97 | gpio_write_bit(CFG_GPIO_FLASH_WP, 1); | |
98 | ||
54fd6c93 SR |
99 | /* |
100 | * Reset PHY's: | |
101 | * The PHY's need a 2nd reset pulse, since the MDIO address is latched | |
102 | * upon reset, and with the first reset upon powerup, the addresses are | |
103 | * not latched reliable, since the IRQ line is multiplexed with an | |
104 | * MDIO address. A 2nd reset at this time will make sure, that the | |
105 | * correct address is latched. | |
106 | */ | |
107 | gpio_write_bit(CFG_GPIO_PHY0_RST, 1); | |
108 | gpio_write_bit(CFG_GPIO_PHY1_RST, 1); | |
109 | udelay(1000); | |
110 | gpio_write_bit(CFG_GPIO_PHY0_RST, 0); | |
111 | gpio_write_bit(CFG_GPIO_PHY1_RST, 0); | |
112 | udelay(1000); | |
113 | gpio_write_bit(CFG_GPIO_PHY0_RST, 1); | |
114 | gpio_write_bit(CFG_GPIO_PHY1_RST, 1); | |
115 | ||
b765ffb7 SR |
116 | return 0; |
117 | } | |
118 | ||
119 | /*---------------------------------------------------------------------------+ | |
120 | | misc_init_r. | |
121 | +---------------------------------------------------------------------------*/ | |
122 | int misc_init_r(void) | |
123 | { | |
124 | u32 pbcr; | |
125 | int size_val = 0; | |
126 | u32 reg; | |
127 | unsigned long usb2d0cr = 0; | |
128 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
129 | unsigned long sdr0_pfc1; | |
130 | ||
131 | /* | |
132 | * FLASH stuff... | |
133 | */ | |
134 | ||
135 | /* Re-do sizing to get full correct info */ | |
136 | ||
137 | /* adjust flash start and offset */ | |
138 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
139 | gd->bd->bi_flashoffset = 0; | |
140 | ||
141 | mfebc(pb0cr, pbcr); | |
142 | switch (gd->bd->bi_flashsize) { | |
143 | case 1 << 20: | |
144 | size_val = 0; | |
145 | break; | |
146 | case 2 << 20: | |
147 | size_val = 1; | |
148 | break; | |
149 | case 4 << 20: | |
150 | size_val = 2; | |
151 | break; | |
152 | case 8 << 20: | |
153 | size_val = 3; | |
154 | break; | |
155 | case 16 << 20: | |
156 | size_val = 4; | |
157 | break; | |
158 | case 32 << 20: | |
159 | size_val = 5; | |
160 | break; | |
161 | case 64 << 20: | |
162 | size_val = 6; | |
163 | break; | |
164 | case 128 << 20: | |
165 | size_val = 7; | |
166 | break; | |
167 | } | |
168 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); | |
169 | mtebc(pb0cr, pbcr); | |
170 | ||
171 | /* | |
172 | * Re-check to get correct base address | |
173 | */ | |
174 | flash_get_size(gd->bd->bi_flashstart, 0); | |
175 | ||
176 | /* Monitor protection ON by default */ | |
177 | (void)flash_protect(FLAG_PROTECT_SET, | |
178 | -CFG_MONITOR_LEN, | |
179 | 0xffffffff, | |
9f24a808 | 180 | &flash_info[1]); |
b765ffb7 SR |
181 | |
182 | /* Env protection ON by default */ | |
183 | (void)flash_protect(FLAG_PROTECT_SET, | |
184 | CFG_ENV_ADDR_REDUND, | |
185 | CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, | |
9f24a808 | 186 | &flash_info[1]); |
b765ffb7 SR |
187 | |
188 | /* | |
189 | * USB suff... | |
190 | */ | |
191 | /* SDR Setting */ | |
192 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
193 | mfsdr(SDR0_USB0, usb2d0cr); | |
194 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
195 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
196 | ||
197 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
198 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
199 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; | |
200 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ | |
201 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
202 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ | |
203 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
204 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ | |
205 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
206 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ | |
207 | ||
208 | /* An 8-bit/60MHz interface is the only possible alternative | |
209 | when connecting the Device to the PHY */ | |
210 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
211 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ | |
212 | ||
213 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
214 | mtsdr(SDR0_USB0, usb2d0cr); | |
215 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
216 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
217 | ||
218 | /* | |
219 | * Clear resets | |
220 | */ | |
221 | udelay (1000); | |
222 | mtsdr(SDR0_SRST1, 0x00000000); | |
223 | udelay (1000); | |
224 | mtsdr(SDR0_SRST0, 0x00000000); | |
225 | ||
226 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
227 | ||
228 | /* | |
229 | * Clear PLB4A0_ACR[WRP] | |
230 | * This fix will make the MAL burst disabling patch for the Linux | |
231 | * EMAC driver obsolete. | |
232 | */ | |
233 | reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; | |
234 | mtdcr(plb4_acr, reg); | |
235 | ||
3ad63878 SR |
236 | /* |
237 | * Init matrix keyboard | |
238 | */ | |
239 | misc_init_r_kbd(); | |
240 | ||
b765ffb7 SR |
241 | return 0; |
242 | } | |
243 | ||
244 | int checkboard(void) | |
245 | { | |
246 | char *s = getenv("serial#"); | |
247 | ||
248 | printf("Board: lwmon5"); | |
249 | ||
250 | if (s != NULL) { | |
251 | puts(", serial# "); | |
252 | puts(s); | |
253 | } | |
254 | putc('\n'); | |
255 | ||
256 | return (0); | |
257 | } | |
258 | ||
259 | #if defined(CFG_DRAM_TEST) | |
260 | int testdram(void) | |
261 | { | |
262 | unsigned long *mem = (unsigned long *)0; | |
263 | const unsigned long kend = (1024 / sizeof(unsigned long)); | |
264 | unsigned long k, n; | |
265 | ||
266 | mtmsr(0); | |
267 | ||
268 | for (k = 0; k < CFG_MBYTES_SDRAM; | |
269 | ++k, mem += (1024 / sizeof(unsigned long))) { | |
270 | if ((k & 1023) == 0) { | |
271 | printf("%3d MB\r", k / 1024); | |
272 | } | |
273 | ||
274 | memset(mem, 0xaaaaaaaa, 1024); | |
275 | for (n = 0; n < kend; ++n) { | |
276 | if (mem[n] != 0xaaaaaaaa) { | |
277 | printf("SDRAM test fails at: %08x\n", | |
278 | (uint) & mem[n]); | |
279 | return 1; | |
280 | } | |
281 | } | |
282 | ||
283 | memset(mem, 0x55555555, 1024); | |
284 | for (n = 0; n < kend; ++n) { | |
285 | if (mem[n] != 0x55555555) { | |
286 | printf("SDRAM test fails at: %08x\n", | |
287 | (uint) & mem[n]); | |
288 | return 1; | |
289 | } | |
290 | } | |
291 | } | |
292 | printf("SDRAM test passes\n"); | |
293 | return 0; | |
294 | } | |
295 | #endif | |
296 | ||
297 | /************************************************************************* | |
298 | * pci_pre_init | |
299 | * | |
300 | * This routine is called just prior to registering the hose and gives | |
301 | * the board the opportunity to check things. Returning a value of zero | |
302 | * indicates that things are bad & PCI initialization should be aborted. | |
303 | * | |
304 | * Different boards may wish to customize the pci controller structure | |
305 | * (add regions, override default access routines, etc) or perform | |
306 | * certain pre-initialization actions. | |
307 | * | |
308 | ************************************************************************/ | |
466fff1a | 309 | #if defined(CONFIG_PCI) |
b765ffb7 SR |
310 | int pci_pre_init(struct pci_controller *hose) |
311 | { | |
312 | unsigned long addr; | |
313 | ||
314 | /*-------------------------------------------------------------------------+ | |
315 | | Set priority for all PLB3 devices to 0. | |
316 | | Set PLB3 arbiter to fair mode. | |
317 | +-------------------------------------------------------------------------*/ | |
318 | mfsdr(sdr_amp1, addr); | |
319 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
320 | addr = mfdcr(plb3_acr); | |
321 | mtdcr(plb3_acr, addr | 0x80000000); | |
322 | ||
323 | /*-------------------------------------------------------------------------+ | |
324 | | Set priority for all PLB4 devices to 0. | |
325 | +-------------------------------------------------------------------------*/ | |
326 | mfsdr(sdr_amp0, addr); | |
327 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
328 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
329 | mtdcr(plb4_acr, addr); | |
330 | ||
331 | /*-------------------------------------------------------------------------+ | |
332 | | Set Nebula PLB4 arbiter to fair mode. | |
333 | +-------------------------------------------------------------------------*/ | |
334 | /* Segment0 */ | |
335 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
336 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
337 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
338 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
339 | mtdcr(plb0_acr, addr); | |
340 | ||
341 | /* Segment1 */ | |
342 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
343 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
344 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
345 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
346 | mtdcr(plb1_acr, addr); | |
347 | ||
348 | return 1; | |
349 | } | |
466fff1a | 350 | #endif /* defined(CONFIG_PCI) */ |
b765ffb7 SR |
351 | |
352 | /************************************************************************* | |
353 | * pci_target_init | |
354 | * | |
355 | * The bootstrap configuration provides default settings for the pci | |
356 | * inbound map (PIM). But the bootstrap config choices are limited and | |
357 | * may not be sufficient for a given board. | |
358 | * | |
359 | ************************************************************************/ | |
360 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) | |
361 | void pci_target_init(struct pci_controller *hose) | |
362 | { | |
363 | /*--------------------------------------------------------------------------+ | |
364 | * Set up Direct MMIO registers | |
365 | *--------------------------------------------------------------------------*/ | |
366 | /*--------------------------------------------------------------------------+ | |
367 | | PowerPC440EPX PCI Master configuration. | |
368 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
369 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF | |
370 | | Use byte reversed out routines to handle endianess. | |
371 | | Make this region non-prefetchable. | |
372 | +--------------------------------------------------------------------------*/ | |
373 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
374 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ | |
375 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ | |
376 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
377 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
378 | ||
379 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
380 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ | |
381 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ | |
382 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
383 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
384 | ||
385 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
386 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ | |
387 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
388 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
389 | ||
390 | /*--------------------------------------------------------------------------+ | |
391 | * Set up Configuration registers | |
392 | *--------------------------------------------------------------------------*/ | |
393 | ||
394 | /* Program the board's subsystem id/vendor id */ | |
395 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
396 | CFG_PCI_SUBSYS_VENDORID); | |
397 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); | |
398 | ||
399 | /* Configure command register as bus master */ | |
400 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
401 | ||
402 | /* 240nS PCI clock */ | |
403 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
404 | ||
405 | /* No error reporting */ | |
406 | pci_write_config_word(0, PCI_ERREN, 0); | |
407 | ||
408 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
409 | ||
410 | } | |
411 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ | |
412 | ||
413 | /************************************************************************* | |
414 | * pci_master_init | |
415 | * | |
416 | ************************************************************************/ | |
417 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) | |
418 | void pci_master_init(struct pci_controller *hose) | |
419 | { | |
420 | unsigned short temp_short; | |
421 | ||
422 | /*--------------------------------------------------------------------------+ | |
423 | | Write the PowerPC440 EP PCI Configuration regs. | |
424 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
425 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
426 | +--------------------------------------------------------------------------*/ | |
427 | pci_read_config_word(0, PCI_COMMAND, &temp_short); | |
428 | pci_write_config_word(0, PCI_COMMAND, | |
429 | temp_short | PCI_COMMAND_MASTER | | |
430 | PCI_COMMAND_MEMORY); | |
431 | } | |
432 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ | |
433 | ||
434 | /************************************************************************* | |
435 | * is_pci_host | |
436 | * | |
437 | * This routine is called to determine if a pci scan should be | |
438 | * performed. With various hardware environments (especially cPCI and | |
439 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
440 | * bit in the strap register, or generic host/adapter assumptions. | |
441 | * | |
442 | * Rather than hard-code a bad assumption in the general 440 code, the | |
443 | * 440 pci code requires the board to decide at runtime. | |
444 | * | |
445 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
446 | * | |
447 | * | |
448 | ************************************************************************/ | |
449 | #if defined(CONFIG_PCI) | |
450 | int is_pci_host(struct pci_controller *hose) | |
451 | { | |
452 | /* Cactus is always configured as host. */ | |
453 | return (1); | |
454 | } | |
455 | #endif /* defined(CONFIG_PCI) */ | |
456 | ||
457 | void hw_watchdog_reset(void) | |
458 | { | |
459 | int val; | |
460 | ||
461 | /* | |
462 | * Toggle watchdog output | |
463 | */ | |
464 | val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; | |
465 | gpio_write_bit(CFG_GPIO_WATCHDOG, val); | |
466 | } | |
c25dd8fc SR |
467 | |
468 | int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
469 | { | |
470 | if (argc < 2) { | |
471 | printf("Usage:\n%s\n", cmdtp->usage); | |
472 | return 1; | |
473 | } | |
474 | ||
475 | if ((strcmp(argv[1], "on") == 0)) { | |
476 | gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1); | |
477 | } else if ((strcmp(argv[1], "off") == 0)) { | |
478 | gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0); | |
479 | } else { | |
480 | printf("Usage:\n%s\n", cmdtp->usage); | |
481 | return 1; | |
482 | } | |
483 | ||
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | U_BOOT_CMD( | |
489 | eepromwp, 2, 0, do_eeprom_wp, | |
490 | "eepromwp- eeprom write protect off/on\n", | |
491 | "<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n" | |
492 | ); | |
d610a607 AG |
493 | |
494 | #if defined(CONFIG_VIDEO) | |
495 | #include <video_fb.h> | |
496 | #include <mb862xx.h> | |
497 | ||
498 | extern GraphicDevice mb862xx; | |
499 | ||
500 | static const gdc_regs init_regs [] = | |
501 | { | |
502 | {0x0100, 0x00000f00}, | |
503 | {0x0020, 0x801401df}, | |
504 | {0x0024, 0x00000000}, | |
505 | {0x0028, 0x00000000}, | |
506 | {0x002c, 0x00000000}, | |
507 | {0x0110, 0x00000000}, | |
508 | {0x0114, 0x00000000}, | |
509 | {0x0118, 0x01df0280}, | |
510 | {0x0004, 0x031f0000}, | |
511 | {0x0008, 0x027f027f}, | |
512 | {0x000c, 0x015f028f}, | |
513 | {0x0010, 0x020c0000}, | |
514 | {0x0014, 0x01df01ea}, | |
515 | {0x0018, 0x00000000}, | |
516 | {0x001c, 0x01e00280}, | |
517 | {0x0100, 0x80010f00}, | |
518 | {0x0, 0x0} | |
519 | }; | |
520 | ||
521 | const gdc_regs *board_get_regs (void) | |
522 | { | |
523 | return init_regs; | |
524 | } | |
525 | ||
526 | /* Returns Lime base address */ | |
527 | unsigned int board_video_init (void) | |
528 | { | |
529 | /* | |
530 | * Reset Lime controller | |
531 | */ | |
532 | gpio_write_bit(CFG_GPIO_LIME_S, 1); | |
533 | udelay(500); | |
534 | gpio_write_bit(CFG_GPIO_LIME_RST, 1); | |
535 | ||
536 | /* Lime memory clock adjusted to 100MHz */ | |
537 | out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ); | |
538 | /* Wait untill time expired. Because of requirements in lime manual */ | |
539 | udelay(300); | |
540 | /* Write lime controller memory parameters */ | |
541 | out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); | |
542 | ||
543 | mb862xx.winSizeX = 640; | |
544 | mb862xx.winSizeY = 480; | |
545 | mb862xx.gdfBytesPP = 2; | |
546 | mb862xx.gdfIndex = GDF_15BIT_555RGB; | |
547 | ||
548 | return CFG_LIME_BASE_0; | |
549 | } | |
550 | ||
551 | void board_backlight_switch (int flag) | |
552 | { | |
553 | if (flag) { | |
554 | /* pwm duty, lamp on */ | |
555 | out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x64); | |
556 | out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701); | |
557 | } else { | |
558 | /* lamp off */ | |
559 | out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x00); | |
560 | out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x00); | |
561 | } | |
562 | } | |
563 | ||
564 | #if defined(CONFIG_CONSOLE_EXTRA_INFO) | |
565 | /* | |
566 | * Return text to be printed besides the logo. | |
567 | */ | |
568 | void video_get_info_str (int line_number, char *info) | |
569 | { | |
570 | if (line_number == 1) { | |
571 | strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); | |
572 | } else { | |
573 | info [0] = '\0'; | |
574 | } | |
575 | } | |
576 | #endif | |
577 | #endif /* CONFIG_VIDEO */ |