]>
Commit | Line | Data |
---|---|---|
78b123cd MB |
1 | /* |
2 | * (C) Copyright 2000-2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/m5271.h> | |
26 | #include <asm/immap_5271.h> | |
27 | ||
28 | int checkboard (void) { | |
29 | puts ("Board: Freescale M5271EVB\n"); | |
30 | return 0; | |
31 | }; | |
32 | ||
33 | long int initdram (int board_type) { | |
34 | ||
35 | int i; | |
36 | ||
37 | /* Enable Address lines 23-21 and lower 16bits of data path */ | |
38 | mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 | | |
39 | MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 | | |
40 | MCF_GPIO_AD_DATAL); | |
41 | ||
42 | /* Set CS2 pin to be SD_CS0 */ | |
43 | mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) | |
44 | | MCF_GPIO_PAR_CS_PAR_CS2); | |
45 | ||
46 | /* Configure SDRAM Control Pin Assignemnt Register */ | |
47 | mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 | | |
48 | MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | | |
49 | MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | | |
50 | MCF_GPIO_SDRAM_SDCS_11); | |
51 | ||
52 | /* | |
53 | * Check to see if the SDRAM has already been initialized | |
54 | * by a run control tool | |
55 | */ | |
977b50f8 | 56 | if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { |
78b123cd | 57 | /* Initialize DRAM Control Register: DCR */ |
977b50f8 | 58 | mbar_writeShort(MCF_SDRAMC_DCR, |
78b123cd MB |
59 | MCF_SDRAMC_DCR_RTIM(0x01) |
60 | | MCF_SDRAMC_DCR_RC(0x30)); | |
61 | ||
62 | /* | |
63 | * Initialize DACR0 | |
64 | * | |
65 | * CASL: 01 | |
66 | * CBM: cmd at A20, bank select bits 21 and up | |
67 | * PS: 32bit port size | |
68 | */ | |
69 | mbar_writeLong(MCF_SDRAMC_DACR0, | |
70 | MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) | |
71 | | MCF_SDRAMC_DACRn_CASL(1) | |
72 | | MCF_SDRAMC_DACRn_CBM(3) | |
73 | | MCF_SDRAMC_DACRn_PS(0)); | |
74 | ||
75 | /* Initialize DMR0 */ | |
977b50f8 | 76 | mbar_writeLong(MCF_SDRAMC_DMR0, |
78b123cd MB |
77 | MCF_SDRAMC_DMRn_BAM_16M |
78 | | MCF_SDRAMC_DMRn_V); | |
79 | ||
80 | /* Set IP bit in DACR */ | |
81 | mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | |
82 | | MCF_SDRAMC_DACRn_IP); | |
83 | ||
84 | /* Wait at least 20ns to allow banks to precharge */ | |
85 | for (i = 0; i < 5; i++) | |
86 | asm(" nop"); | |
87 | ||
88 | /* Write to this block to initiate precharge */ | |
89 | *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5; | |
90 | ||
91 | /* Set RE bit in DACR */ | |
92 | mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | |
93 | | MCF_SDRAMC_DACRn_RE); | |
94 | ||
95 | /* Wait for at least 8 auto refresh cycles to occur */ | |
96 | for (i = 0; i < 2000; i++) | |
97 | asm(" nop"); | |
98 | ||
99 | /* Finish the configuration by issuing the MRS */ | |
100 | mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | |
101 | | MCF_SDRAMC_DACRn_MRS); | |
102 | ||
103 | /* | |
104 | * Write to the SDRAM Mode Register A0-A11 = 0x400 | |
105 | * | |
106 | * Write Burst Mode = Programmed Burst Length | |
107 | * Op Mode = Standard Op | |
108 | * CAS Latency = 2 | |
109 | * Burst Type = Sequential | |
110 | * Burst Length = 1 | |
111 | */ | |
112 | *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5; | |
113 | } | |
114 | ||
115 | return CFG_SDRAM_SIZE * 1024 * 1024; | |
116 | }; | |
117 | ||
118 | int testdram (void) { | |
119 | ||
120 | /* TODO: XXX XXX XXX */ | |
121 | printf ("DRAM test not implemented!\n"); | |
122 | ||
123 | return (0); | |
124 | } |