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a87589da | 1 | /* |
3515fd18 | 2 | * (C) Copyright 2003-2008 |
a87589da WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
8 | * (C) Copyright 2004 | |
9 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
10 | * | |
3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
a87589da WD |
12 | */ |
13 | ||
14 | #include <common.h> | |
15 | #include <mpc5xxx.h> | |
16 | #include <pci.h> | |
3515fd18 | 17 | #include <asm/processor.h> |
6d51e505 | 18 | #include <malloc.h> |
a87589da | 19 | |
6d0f6bcf | 20 | #ifndef CONFIG_SYS_RAMBOOT |
a87589da WD |
21 | static void sdram_start (int hi_addr) |
22 | { | |
23 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
24 | ||
25 | /* unlock mode register */ | |
26 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; | |
27 | __asm__ volatile ("sync"); | |
28 | ||
29 | /* precharge all banks */ | |
30 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; | |
31 | __asm__ volatile ("sync"); | |
32 | ||
33 | #if SDRAM_DDR | |
34 | /* set mode register: extended mode */ | |
35 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; | |
36 | __asm__ volatile ("sync"); | |
37 | ||
38 | /* set mode register: reset DLL */ | |
39 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; | |
40 | __asm__ volatile ("sync"); | |
41 | #endif | |
42 | ||
43 | /* precharge all banks */ | |
44 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; | |
45 | __asm__ volatile ("sync"); | |
46 | ||
47 | /* auto refresh */ | |
48 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; | |
49 | __asm__ volatile ("sync"); | |
50 | ||
51 | /* set mode register */ | |
52 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; | |
53 | __asm__ volatile ("sync"); | |
54 | ||
55 | /* normal operation */ | |
56 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; | |
57 | __asm__ volatile ("sync"); | |
58 | } | |
59 | #endif | |
60 | ||
61 | /* | |
62 | * ATTENTION: Although partially referenced initdram does NOT make real use | |
6d0f6bcf | 63 | * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE |
a87589da WD |
64 | * is something else than 0x00000000. |
65 | */ | |
66 | ||
9973e3c6 | 67 | phys_size_t initdram (int board_type) |
a87589da WD |
68 | { |
69 | ulong dramsize = 0; | |
6d0f6bcf | 70 | #ifndef CONFIG_SYS_RAMBOOT |
a87589da | 71 | ulong test1, test2; |
3515fd18 | 72 | uint svr, pvr; |
a87589da WD |
73 | |
74 | /* setup SDRAM chip selects */ | |
75 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ | |
76 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ | |
77 | __asm__ volatile ("sync"); | |
78 | ||
79 | /* setup config registers */ | |
80 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; | |
81 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; | |
82 | __asm__ volatile ("sync"); | |
83 | ||
84 | #if SDRAM_DDR | |
85 | /* set tap delay */ | |
86 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; | |
87 | __asm__ volatile ("sync"); | |
88 | #endif | |
89 | ||
90 | /* find RAM size using SDRAM CS0 only */ | |
91 | sdram_start(0); | |
6d0f6bcf | 92 | test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); |
a87589da | 93 | sdram_start(1); |
6d0f6bcf | 94 | test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); |
a87589da WD |
95 | if (test1 > test2) { |
96 | sdram_start(0); | |
97 | dramsize = test1; | |
98 | } else { | |
99 | dramsize = test2; | |
100 | } | |
101 | ||
102 | /* memory smaller than 1MB is impossible */ | |
103 | if (dramsize < (1 << 20)) { | |
104 | dramsize = 0; | |
105 | } | |
106 | ||
107 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
108 | if (dramsize > 0) { | |
109 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + | |
110 | __builtin_ffs(dramsize >> 20) - 1; | |
111 | } else { | |
112 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ | |
113 | } | |
114 | ||
115 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ | |
6d0f6bcf | 116 | #else /* CONFIG_SYS_RAMBOOT */ |
a87589da WD |
117 | |
118 | /* retrieve size of memory connected to SDRAM CS0 */ | |
119 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; | |
120 | if (dramsize >= 0x13) { | |
121 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
122 | } else { | |
123 | dramsize = 0; | |
124 | } | |
125 | ||
126 | /* retrieve size of memory connected to SDRAM CS1 */ | |
127 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; | |
128 | if (dramsize2 >= 0x13) { | |
129 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | |
130 | } else { | |
131 | dramsize2 = 0; | |
132 | } | |
133 | ||
6d0f6bcf | 134 | #endif /* CONFIG_SYS_RAMBOOT */ |
a87589da | 135 | |
c6dc21c8 WD |
136 | /* |
137 | * On MPC5200B we need to set the special configuration delay in the | |
138 | * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM | |
139 | * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: | |
140 | * | |
141 | * "The SDelay should be written to a value of 0x00000004. It is | |
142 | * required to account for changes caused by normal wafer processing | |
143 | * parameters." | |
144 | */ | |
145 | svr = get_svr(); | |
146 | pvr = get_pvr(); | |
147 | if ((SVR_MJREV(svr) >= 2) && | |
148 | (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { | |
149 | ||
150 | *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; | |
151 | __asm__ volatile ("sync"); | |
152 | } | |
153 | ||
a87589da WD |
154 | /* return dramsize + dramsize2; */ |
155 | return dramsize; | |
156 | } | |
157 | ||
158 | int checkboard (void) | |
159 | { | |
160 | puts ("Board: HMI1001\n"); | |
161 | return 0; | |
162 | } | |
163 | ||
9f96ae44 WD |
164 | #ifdef CONFIG_PREBOOT |
165 | ||
166 | static uchar kbd_magic_prefix[] = "key_magic"; | |
167 | static uchar kbd_command_prefix[] = "key_cmd"; | |
168 | ||
169 | #define S1_ROT 0xf0 | |
170 | #define S2_Q 0x40 | |
171 | #define S2_M 0x20 | |
172 | ||
173 | struct kbd_data_t { | |
174 | char s1; | |
175 | char s2; | |
176 | }; | |
177 | ||
178 | struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) | |
179 | { | |
6d0f6bcf JCPV |
180 | kbd_data->s1 = *((volatile uchar*)(CONFIG_SYS_STATUS1_BASE)); |
181 | kbd_data->s2 = *((volatile uchar*)(CONFIG_SYS_STATUS2_BASE)); | |
9f96ae44 WD |
182 | |
183 | return kbd_data; | |
184 | } | |
185 | ||
8d7e2732 | 186 | static int compare_magic (const struct kbd_data_t *kbd_data, char *str) |
9f96ae44 WD |
187 | { |
188 | char s1 = str[0]; | |
189 | char s2; | |
190 | ||
191 | if (s1 >= '0' && s1 <= '9') | |
192 | s1 -= '0'; | |
193 | else if (s1 >= 'a' && s1 <= 'f') | |
194 | s1 = s1 - 'a' + 10; | |
195 | else if (s1 >= 'A' && s1 <= 'F') | |
196 | s1 = s1 - 'A' + 10; | |
197 | else | |
198 | return -1; | |
199 | ||
200 | if (((S1_ROT & kbd_data->s1) >> 4) != s1) | |
201 | return -1; | |
202 | ||
203 | s2 = (S2_Q | S2_M) & kbd_data->s2; | |
204 | ||
205 | switch (str[1]) { | |
206 | case 'q': | |
207 | case 'Q': | |
208 | if (s2 == S2_Q) | |
209 | return -1; | |
210 | break; | |
211 | case 'm': | |
212 | case 'M': | |
213 | if (s2 == S2_M) | |
214 | return -1; | |
215 | break; | |
216 | case '\0': | |
217 | if (s2 == (S2_Q | S2_M)) | |
218 | return 0; | |
219 | default: | |
220 | return -1; | |
221 | } | |
222 | ||
223 | if (str[2]) | |
224 | return -1; | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
8d7e2732 | 229 | static char *key_match (const struct kbd_data_t *kbd_data) |
9f96ae44 | 230 | { |
8d7e2732 WD |
231 | char magic[sizeof (kbd_magic_prefix) + 1]; |
232 | char *suffix; | |
233 | char *kbd_magic_keys; | |
9f96ae44 WD |
234 | |
235 | /* | |
236 | * The following string defines the characters that can be appended | |
237 | * to "key_magic" to form the names of environment variables that | |
238 | * hold "magic" key codes, i. e. such key codes that can cause | |
239 | * pre-boot actions. If the string is empty (""), then only | |
240 | * "key_magic" is checked (old behaviour); the string "125" causes | |
241 | * checks for "key_magic1", "key_magic2" and "key_magic5", etc. | |
242 | */ | |
243 | if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) | |
244 | kbd_magic_keys = ""; | |
245 | ||
246 | /* loop over all magic keys; | |
247 | * use '\0' suffix in case of empty string | |
248 | */ | |
249 | for (suffix = kbd_magic_keys; *suffix || | |
250 | suffix == kbd_magic_keys; ++suffix) { | |
251 | sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); | |
252 | ||
253 | if (compare_magic(kbd_data, getenv(magic)) == 0) { | |
8d7e2732 | 254 | char cmd_name[sizeof (kbd_command_prefix) + 1]; |
9f96ae44 WD |
255 | char *cmd; |
256 | ||
257 | sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); | |
258 | cmd = getenv (cmd_name); | |
259 | ||
260 | return (cmd); | |
261 | } | |
262 | } | |
263 | ||
264 | return (NULL); | |
265 | } | |
266 | ||
267 | #endif /* CONFIG_PREBOOT */ | |
268 | ||
9f96ae44 WD |
269 | int misc_init_r (void) |
270 | { | |
271 | #ifdef CONFIG_PREBOOT | |
272 | struct kbd_data_t kbd_data; | |
273 | /* Decode keys */ | |
8d7e2732 | 274 | char *str = strdup (key_match (get_keys (&kbd_data))); |
9f96ae44 WD |
275 | /* Set or delete definition */ |
276 | setenv ("preboot", str); | |
277 | free (str); | |
278 | #endif /* CONFIG_PREBOOT */ | |
279 | ||
a87589da WD |
280 | return 0; |
281 | } | |
282 | ||
283 | int board_early_init_r (void) | |
284 | { | |
285 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ | |
286 | *(vu_long *)MPC5XXX_BOOTCS_START = | |
6d0f6bcf | 287 | *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE); |
a87589da | 288 | *(vu_long *)MPC5XXX_BOOTCS_STOP = |
6d0f6bcf | 289 | *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE); |
a87589da WD |
290 | return 0; |
291 | } | |
98128f38 WD |
292 | #ifdef CONFIG_PCI |
293 | static struct pci_controller hose; | |
294 | ||
295 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
296 | ||
297 | void pci_init_board(void) | |
298 | { | |
299 | pci_mpc5xxx_init(&hose); | |
300 | } | |
301 | #endif |