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7fb3e7a2 AS |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * Keith Outwater, keith_outwater@mvis.com. | |
5 | * | |
6 | * (C) Copyright 2011 | |
7 | * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
7fb3e7a2 AS |
10 | */ |
11 | ||
12 | #include <common.h> | |
13 | #include <ACEX1K.h> | |
14 | #include <command.h> | |
15 | #include "mergerbox.h" | |
16 | #include "fpga.h" | |
17 | ||
18 | Altera_CYC2_Passive_Serial_fns altera_fns = { | |
19 | fpga_null_fn, | |
20 | fpga_config_fn, | |
21 | fpga_status_fn, | |
22 | fpga_done_fn, | |
23 | fpga_wr_fn, | |
24 | fpga_null_fn, | |
25 | fpga_null_fn, | |
26 | }; | |
27 | ||
28 | Altera_desc cyclone2 = { | |
29 | Altera_CYC2, | |
30 | passive_serial, | |
31 | Altera_EP2C20_SIZE, | |
32 | (void *) &altera_fns, | |
33 | NULL, | |
34 | 0 | |
35 | }; | |
36 | ||
37 | DECLARE_GLOBAL_DATA_PTR; | |
38 | ||
39 | int mergerbox_init_fpga(void) | |
40 | { | |
41 | debug("Initialize FPGA interface\n"); | |
42 | fpga_init(); | |
43 | fpga_add(fpga_altera, &cyclone2); | |
44 | ||
45 | return 1; | |
46 | } | |
47 | ||
48 | int fpga_null_fn(int cookie) | |
49 | { | |
50 | return 0; | |
51 | } | |
52 | ||
53 | int fpga_config_fn(int assert, int flush, int cookie) | |
54 | { | |
55 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
56 | volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; | |
57 | u32 dvo = gpio->dat; | |
58 | ||
59 | dvo &= ~FPGA_CONFIG; | |
60 | gpio->dat = dvo; | |
61 | udelay(5); | |
62 | dvo |= FPGA_CONFIG; | |
63 | gpio->dat = dvo; | |
64 | ||
65 | return assert; | |
66 | } | |
67 | ||
68 | int fpga_done_fn(int cookie) | |
69 | { | |
70 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
71 | volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; | |
72 | int result = 0; | |
73 | ||
74 | udelay(10); | |
75 | debug("CONF_DONE check ... "); | |
76 | if (gpio->dat & FPGA_CONF_DONE) { | |
77 | debug("high\n"); | |
78 | result = 1; | |
79 | } else | |
80 | debug("low\n"); | |
81 | ||
82 | return result; | |
83 | } | |
84 | ||
85 | int fpga_status_fn(int cookie) | |
86 | { | |
87 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
88 | volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; | |
89 | int result = 0; | |
90 | ||
91 | debug("STATUS check ... "); | |
92 | if (gpio->dat & FPGA_STATUS) { | |
93 | debug("high\n"); | |
94 | result = 1; | |
95 | } else | |
96 | debug("low\n"); | |
97 | ||
98 | return result; | |
99 | } | |
100 | ||
101 | int fpga_clk_fn(int assert_clk, int flush, int cookie) | |
102 | { | |
103 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
104 | volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; | |
105 | u32 dvo = gpio->dat; | |
106 | ||
107 | debug("CLOCK %s\n", assert_clk ? "high" : "low"); | |
108 | if (assert_clk) | |
109 | dvo |= FPGA_CCLK; | |
110 | else | |
111 | dvo &= ~FPGA_CCLK; | |
112 | ||
113 | if (flush) | |
114 | gpio->dat = dvo; | |
115 | ||
116 | return assert_clk; | |
117 | } | |
118 | ||
119 | static inline int _write_fpga(u8 val, int dump) | |
120 | { | |
121 | volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; | |
122 | volatile gpio83xx_t *gpio = (gpio83xx_t *)&im->gpio[0]; | |
123 | int i; | |
124 | u32 dvo = gpio->dat; | |
125 | ||
126 | if (dump) | |
127 | debug(" %02x -> ", val); | |
128 | for (i = 0; i < 8; i++) { | |
129 | dvo &= ~FPGA_CCLK; | |
130 | gpio->dat = dvo; | |
131 | dvo &= ~FPGA_DIN; | |
132 | if (dump) | |
133 | debug("%d ", val&1); | |
134 | if (val & 1) | |
135 | dvo |= FPGA_DIN; | |
136 | gpio->dat = dvo; | |
137 | dvo |= FPGA_CCLK; | |
138 | gpio->dat = dvo; | |
139 | val >>= 1; | |
140 | } | |
141 | if (dump) | |
142 | debug("\n"); | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
e6a857da | 147 | int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) |
7fb3e7a2 AS |
148 | { |
149 | unsigned char *data = (unsigned char *) buf; | |
150 | int i; | |
151 | ||
152 | debug("fpga_wr: buf %p / size %d\n", buf, len); | |
153 | for (i = 0; i < len; i++) | |
154 | _write_fpga(data[i], 0); | |
155 | debug("\n"); | |
156 | ||
157 | return FPGA_SUCCESS; | |
158 | } |