[thirdparty/u-boot.git] / board / mcc200 / mcc200.c

/*
 * (C) Copyright 2003-2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <asm/processor.h>

/* Two MT48LC8M32B2 for 32 MB */
/* #include "mt48lc8m32b2-6-7.h" */

/* One MT48LC16M32S2 for 64 MB */
/* #include "mt48lc16m32s2-75.h" */
#if defined (CONFIG_MCC200_SDRAM)
#include "mt48lc16m16a2-75.h"
#else
#include "mt46v16m16-75.h"
#endif

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[];	/* FLASH chips info */

extern int do_auto_update(void);
ulong flash_get_size (ulong base, int banknum);

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");

	udelay(10);
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *	      is something else than 0x00000000.
 */

phys_size_t initdram (int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
	uint svr, pvr;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else {
		dramsize2 = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20)) {
		dramsize2 = 0;
	}

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CONFIG_SYS_RAMBOOT */

	/*
	 * On MPC5200B we need to set the special configuration delay in the
	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	 *
	 * "The SDelay should be written to a value of 0x00000004. It is
	 * required to account for changes caused by normal wafer processing
	 * parameters."
	 */
	svr = get_svr();
	pvr = get_pvr();
	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
		__asm__ volatile ("sync");
	}

	return dramsize + dramsize2;
}

int checkboard (void)
{
#if defined(CONFIG_PRS200)
	puts ("Board: PRS200\n");
#else
	puts ("Board: MCC200\n");
#endif
	return 0;
}

int misc_init_r (void)
{
	ulong flash_sup_end, snum;

	/*
	 * Adjust flash start and offset to detected values
	 */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Check if boot FLASH isn't max size
	 */
	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
		/* adjust mapping */
		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
			START_REG(gd->bd->bi_flashstart);
		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
			STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);

		/*
		 * Re-check to get correct base address
		 */
		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);

		/*
		 * Re-do flash protection upon new addresses
		 */
		flash_protect (FLAG_PROTECT_CLEAR,
			       gd->bd->bi_flashstart, 0xffffffff,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Monitor protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_ENV_ADDR,
			       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);

		/* Redundant environment protection ON by default */
		flash_protect (FLAG_PROTECT_SET,
			       CONFIG_ENV_ADDR_REDUND,
			       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
	}

	if (gd->bd->bi_flashsize > (32 << 20)) {
		/* Unprotect the upper bank of the Flash */
		*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
		flash_protect (FLAG_PROTECT_CLEAR,
			       flash_info[0].start[0] + flash_info[0].size / 2,
			       (flash_info[0].start[0] - 1) + flash_info[0].size,
			       &flash_info[0]);
		*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
		printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
		flash_info[0].size = 32 << 20;
		for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
			flash_info[0].start[snum] < flash_sup_end;
			snum++);
		flash_info[0].sector_count = snum;
	}

#ifdef CONFIG_AUTO_UPDATE
	do_auto_update();
#endif
	return (0);
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)

void init_ide_reset (void)
{
	debug ("init_ide_reset\n");

}

void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

}
#endif

#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
	doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif
Commit	Line	Data
86ea5f93 WD	1	/*
	2	* (C) Copyright 2003-2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
86ea5f93 WD	9	*/
	10
	11	#include <common.h>
	12	#include <mpc5xxx.h>
	13	#include <pci.h>
91650b3e	14	#include <asm/processor.h>
86ea5f93	15
9e18a4bc WD	16	/* Two MT48LC8M32B2 for 32 MB */
	17	/* #include "mt48lc8m32b2-6-7.h" */
	18
	19	/* One MT48LC16M32S2 for 64 MB */
4819fad9 WD	20	/* #include "mt48lc16m32s2-75.h" */
	21	#if defined (CONFIG_MCC200_SDRAM)
	22	#include "mt48lc16m16a2-75.h"
	23	#else
	24	#include "mt46v16m16-75.h"
	25	#endif
86ea5f93	26
d87080b7 WD	27	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	28
58ad4978 SR	29	extern flash_info_t flash_info[]; /* FLASH chips info */
58ad4978 SR	30
cdb97a66	31	extern int do_auto_update(void);
f18e874a SR	32	ulong flash_get_size (ulong base, int banknum);
f18e874a SR	33
6d0f6bcf	34	#ifndef CONFIG_SYS_RAMBOOT
86ea5f93 WD	35	static void sdram_start (int hi_addr)
	36	{
	37	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	38
	39	/* unlock mode register */
	40	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	41	__asm__ volatile ("sync");
	42
	43	/* precharge all banks */
	44	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	45	__asm__ volatile ("sync");
	46
	47	#if SDRAM_DDR
	48	/* set mode register: extended mode */
	49	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	50	__asm__ volatile ("sync");
	51
	52	/* set mode register: reset DLL */
	53	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	54	__asm__ volatile ("sync");
	55	#endif
	56
	57	/* precharge all banks */
	58	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	59	__asm__ volatile ("sync");
	60
	61	/* auto refresh */
	62	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	63	__asm__ volatile ("sync");
	64
	65	/* set mode register */
	66	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	67	__asm__ volatile ("sync");
	68
	69	/* normal operation */
	70	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	71	__asm__ volatile ("sync");
9e18a4bc WD	72
9e18a4bc WD	73	udelay(10);
86ea5f93 WD	74	}
	75	#endif
	76
	77	/*
	78	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	79	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
f11033e7	80	* is something else than 0x00000000.
86ea5f93 WD	81	*/
86ea5f93 WD	82
9973e3c6	83	phys_size_t initdram (int board_type)
86ea5f93 WD	84	{
	85	ulong dramsize = 0;
	86	ulong dramsize2 = 0;
91650b3e	87	uint svr, pvr;
6d0f6bcf	88	#ifndef CONFIG_SYS_RAMBOOT
86ea5f93 WD	89	ulong test1, test2;
	90
	91	/* setup SDRAM chip selects */
	92	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	93	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	94	__asm__ volatile ("sync");
	95
	96	/* setup config registers */
	97	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	98	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	99	__asm__ volatile ("sync");
	100
	101	#if SDRAM_DDR
	102	/* set tap delay */
	103	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	104	__asm__ volatile ("sync");
	105	#endif
	106
	107	/* find RAM size using SDRAM CS0 only */
	108	sdram_start(0);
6d0f6bcf	109	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
86ea5f93	110	sdram_start(1);
6d0f6bcf	111	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
86ea5f93 WD	112	if (test1 > test2) {
	113	sdram_start(0);
	114	dramsize = test1;
	115	} else {
	116	dramsize = test2;
	117	}
	118
	119	/* memory smaller than 1MB is impossible */
	120	if (dramsize < (1 << 20)) {
	121	dramsize = 0;
	122	}
	123
	124	/* set SDRAM CS0 size according to the amount of RAM found */
	125	if (dramsize > 0) {
	126	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	127	} else {
	128	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	129	}
	130
	131	/* let SDRAM CS1 start right after CS0 */
	132	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
	133
	134	/* find RAM size using SDRAM CS1 only */
	135	if (!dramsize)
	136	sdram_start(0);
6d0f6bcf	137	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
86ea5f93 WD	138	if (!dramsize) {
86ea5f93 WD	139	sdram_start(1);
6d0f6bcf	140	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
86ea5f93 WD	141	}
	142	if (test1 > test2) {
	143	sdram_start(0);
	144	dramsize2 = test1;
	145	} else {
	146	dramsize2 = test2;
	147	}
	148
	149	/* memory smaller than 1MB is impossible */
	150	if (dramsize2 < (1 << 20)) {
	151	dramsize2 = 0;
	152	}
	153
	154	/* set SDRAM CS1 size according to the amount of RAM found */
	155	if (dramsize2 > 0) {
	156	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	157	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	158	} else {
	159	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	160	}
	161
6d0f6bcf	162	#else /* CONFIG_SYS_RAMBOOT */
86ea5f93 WD	163
	164	/* retrieve size of memory connected to SDRAM CS0 */
	165	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	166	if (dramsize >= 0x13) {
	167	dramsize = (1 << (dramsize - 0x13)) << 20;
	168	} else {
	169	dramsize = 0;
	170	}
	171
	172	/* retrieve size of memory connected to SDRAM CS1 */
	173	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	174	if (dramsize2 >= 0x13) {
	175	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	176	} else {
	177	dramsize2 = 0;
	178	}
	179
6d0f6bcf	180	#endif /* CONFIG_SYS_RAMBOOT */
86ea5f93	181
91650b3e WD	182	/*
	183	* On MPC5200B we need to set the special configuration delay in the
	184	* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	185	* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	186	*
	187	* "The SDelay should be written to a value of 0x00000004. It is
	188	* required to account for changes caused by normal wafer processing
	189	* parameters."
	190	*/
	191	svr = get_svr();
	192	pvr = get_pvr();
a9398e01	193	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
91650b3e WD	194	(vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;
	195	__asm__ volatile ("sync");
	196	}
	197
86ea5f93 WD	198	return dramsize + dramsize2;
	199	}
	200
86ea5f93 WD	201	int checkboard (void)
86ea5f93 WD	202	{
ed1cf845 WD	203	#if defined(CONFIG_PRS200)
	204	puts ("Board: PRS200\n");
	205	#else
c81eb1f5	206	puts ("Board: MCC200\n");
ed1cf845	207	#endif
86ea5f93 WD	208	return 0;
	209	}
	210
58ad4978	211	int misc_init_r (void)
86ea5f93	212	{
6183bb9e WD	213	ulong flash_sup_end, snum;
6183bb9e WD	214
86ea5f93	215	/*
58ad4978	216	* Adjust flash start and offset to detected values
86ea5f93	217	*/
58ad4978 SR	218	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
58ad4978 SR	219	gd->bd->bi_flashoffset = 0;
86ea5f93	220
58ad4978 SR	221	/*
	222	* Check if boot FLASH isn't max size
	223	*/
6d0f6bcf	224	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
58ad4978 SR	225	/* adjust mapping */
	226	(vu_long )MPC5XXX_BOOTCS_START = (vu_long )MPC5XXX_CS0_START =
	227	START_REG(gd->bd->bi_flashstart);
	228	(vu_long )MPC5XXX_BOOTCS_STOP = (vu_long )MPC5XXX_CS0_STOP =
	229	STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
	230
	231	/*
	232	* Re-check to get correct base address
	233	*/
6d0f6bcf	234	flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
58ad4978 SR	235
	236	/*
	237	* Re-do flash protection upon new addresses
	238	*/
	239	flash_protect (FLAG_PROTECT_CLEAR,
	240	gd->bd->bi_flashstart, 0xffffffff,
6d0f6bcf	241	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
58ad4978 SR	242
	243	/* Monitor protection ON by default */
	244	flash_protect (FLAG_PROTECT_SET,
6d0f6bcf JCPV	245	CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
6d0f6bcf JCPV	246	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
58ad4978 SR	247
	248	/* Environment protection ON by default */
	249	flash_protect (FLAG_PROTECT_SET,
0e8d1586 JCPV	250	CONFIG_ENV_ADDR,
0e8d1586 JCPV	251	CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf	252	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
58ad4978 SR	253
	254	/* Redundant environment protection ON by default */
	255	flash_protect (FLAG_PROTECT_SET,
0e8d1586	256	CONFIG_ENV_ADDR_REDUND,
dfcd7f21	257	CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
6d0f6bcf	258	&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
58ad4978	259	}
86ea5f93	260
3a5e2188 WD	261	if (gd->bd->bi_flashsize > (32 << 20)) {
	262	/* Unprotect the upper bank of the Flash */
	263	(volatile int)MPC5XXX_CS0_CFG \|= (1 << 6);
	264	flash_protect (FLAG_PROTECT_CLEAR,
5d7022b0	265	flash_info[0].start[0] + flash_info[0].size / 2,
985b950a	266	(flash_info[0].start[0] - 1) + flash_info[0].size,
3a5e2188 WD	267	&flash_info[0]);
3a5e2188 WD	268	(volatile int)MPC5XXX_CS0_CFG &= ~(1 << 6);
6183bb9e WD	269	printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
6183bb9e WD	270	flash_info[0].size = 32 << 20;
16850919 WD	271	for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
16850919 WD	272	flash_info[0].start[snum] < flash_sup_end;
6183bb9e WD	273	snum++);
6183bb9e WD	274	flash_info[0].sector_count = snum;
3a5e2188 WD	275	}
3a5e2188 WD	276
787fa158	277	#ifdef CONFIG_AUTO_UPDATE
f11033e7	278	do_auto_update();
787fa158	279	#endif
86ea5f93 WD	280	return (0);
	281	}
	282
	283	#ifdef CONFIG_PCI
	284	static struct pci_controller hose;
	285
	286	extern void pci_mpc5xxx_init(struct pci_controller *);
	287
	288	void pci_init_board(void)
	289	{
	290	pci_mpc5xxx_init(&hose);
	291	}
	292	#endif
	293
d39b5741	294	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
86ea5f93 WD	295
	296	void init_ide_reset (void)
	297	{
	298	debug ("init_ide_reset\n");
	299
	300	}
	301
	302	void ide_set_reset (int idereset)
	303	{
	304	debug ("ide_reset(%d)\n", idereset);
	305
	306	}
d39b5741	307	#endif
86ea5f93	308
3fe00109	309	#if defined(CONFIG_CMD_DOC)
86ea5f93 WD	310	void doc_init (void)
86ea5f93 WD	311	{
6d0f6bcf	312	doc_probe (CONFIG_SYS_DOC_BASE);
86ea5f93 WD	313	}
86ea5f93 WD	314	#endif