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029faf3e SR |
1 | /* |
2 | * (C) Copyright 2009-2010 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
029faf3e SR |
6 | */ |
7 | ||
8 | #include <ppc_asm.tmpl> | |
9 | #include <config.h> | |
10 | #include <asm/mmu.h> | |
550650dd | 11 | #include <asm/ppc4xx.h> |
029faf3e SR |
12 | |
13 | /* | |
14 | * TLB TABLE | |
15 | * | |
16 | * This table is used by the cpu boot code to setup the initial tlb | |
17 | * entries. Rather than make broad assumptions in the cpu source tree, | |
18 | * this table lets each board set things up however they like. | |
19 | * | |
20 | * Pointer to the table is returned in r1 | |
21 | * | |
22 | */ | |
23 | ||
24 | .section .bootpg,"ax" | |
25 | ||
26 | .globl tlbtab | |
27 | tlbtab: | |
28 | tlbtab_start | |
29 | ||
30 | /* | |
31 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to | |
32 | * use the speed up boot process. It is patched after relocation to | |
33 | * enable SA_I. | |
34 | */ | |
35 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, | |
36 | 4, AC_RWX | SA_G) /* TLB 0 */ | |
37 | ||
38 | /* | |
39 | * TLB entries for SDRAM are not needed on this platform. | |
40 | * They are dynamically generated in the SPD DDR(2) detection | |
41 | * routine. | |
42 | */ | |
43 | ||
44 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, | |
45 | AC_RWX | SA_I) | |
46 | ||
47 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, | |
48 | AC_RW | SA_IG) | |
49 | ||
50 | tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, | |
51 | CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H, | |
52 | AC_RW | SA_IG) | |
53 | ||
54 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, | |
55 | AC_RW | SA_IG) | |
56 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, | |
57 | AC_RW | SA_IG) | |
58 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, | |
59 | AC_RW | SA_IG) | |
60 | ||
61 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, | |
62 | AC_RW | SA_IG) | |
63 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, | |
64 | AC_RW | SA_IG) | |
65 | tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, | |
66 | AC_RW | SA_IG) | |
67 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, | |
68 | AC_RW | SA_IG) | |
69 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, | |
70 | AC_RW | SA_IG) | |
71 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, | |
72 | AC_RW | SA_IG) | |
73 | tlbtab_end |