[people/ms/u-boot.git] / board / mpc8260ads / mpc8260ads.c

/*
 * (C) Copyright 2001-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Modified during 2001 by
 * Advanced Communications Technologies (Australia) Pty. Ltd.
 * Howard Walker, Tuong Vu-Dinh
 *
 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
 * Added support for the 16M dram simm on the 8260ads boards
 *
 * (C) Copyright 2003 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include <i2c.h>
#include <spd.h>

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {	/*	      conf ppar psor pdir podr pdat */
        /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
	/* PA6  */ {   1,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
    },

    /* Port B configuration */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
	/* PC10 */ {   1,   1,   0,   0,   0,   0   }, /* LXT970 FETHMDC */
	/* PC9  */ {   1,   1,   0,   0,   0,   0   }, /* LXT970 FETHMDIO */
	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
    },

    /* Port D */
    {   /*	      conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
       /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
       /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};

typedef struct bscr_ {
	unsigned long bcsr0;
	unsigned long bcsr1;
	unsigned long bcsr2;
	unsigned long bcsr3;
	unsigned long bcsr4;
	unsigned long bcsr5;
	unsigned long bcsr6;
	unsigned long bcsr7;
} bcsr_t;

void reset_phy (void)
{
	volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;

	/* reset the FEC port */
	bcsr->bcsr1 &= ~FETH_RST;
	bcsr->bcsr1 |=  FETH_RST;
}


int board_pre_init (void)
{
	volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;

	bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;

	return 0;
}

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)

long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;
	volatile uchar *ramaddr, c = 0xff;

	/* Initialisation is for 16MB DIMM the board is shipped with */
	long int msize = 16;
	uint or    = 0xFF000CA0;
	uint psdmr = CFG_PSDMR;
	uint psrt  = CFG_PSRT;

	int i;

#ifndef CFG_RAMBOOT
	immap->im_siu_conf.sc_ppc_acr  = 0x00000002;
	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
	immap->im_siu_conf.sc_tescr1   = 0x00004000;

	memctl->memc_mptpr = CFG_MPTPR;
	/* init local sdram, bank 4 */
	memctl->memc_lsrt  = 0x00000010;
	memctl->memc_or4   = 0xFFC01480;
	memctl->memc_br4   = 0x04001861;
	memctl->memc_lsdmr = 0x2886A522;
	ramaddr = (uchar *) CFG_LSDRAM_BASE;
	*ramaddr = c;
	memctl->memc_lsdmr = 0x0886A522;
	for (i = 0; i < 8; i++) {
		*ramaddr = c;
	}
	memctl->memc_lsdmr = 0x1886A522;
	*ramaddr = c;
	memctl->memc_lsdmr = 0x4086A522;

	/* init sdram dimm */
#ifdef CONFIG_SPD_EEPROM
	{
		spd_eeprom_t spd;
		uint pbi, bsel, rowst, lsb, tmp;

		i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));

		/* Bank-based interleaving is not supported for physical bank
		   sizes greater than 128MB which is encoded as 0x20 in SPD
		 */
		pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
		msize = spd.nrows * (4 * spd.row_dens);	/* Mixed size not supported */
		or = ~(msize - 1) << 20;	/* SDAM */
		switch (spd.nbanks) {	/* BPD */
		case 2:
			bsel = 1;
			break;
		case 4:
			bsel = 2;
			or |= 0x00002000;
			break;
		case 8:
			bsel = 3;
			or |= 0x00004000;
			break;
		}
		lsb = 3;	/* For 64-bit port, lsb is 3 bits */

		if (pbi) {	/* Bus partition depends on interleaving */
			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
			or |= (rowst << 9);	/* ROWST */
		} else {
			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
			or |= ((rowst * 2 - 12) << 9);	/* ROWST */
		}
		or |= ((spd.nrow_addr - 9) << 6);	/* NUMR */

		psdmr = (pbi << 31);	/* PBI */
		/* Bus multiplexing parameters */
		tmp = 32 - (lsb + spd.nrow_addr);	/* Tables 10-19 and 10-20 */
		psdmr |= ((tmp - (rowst - 5) - 13) << 24);	/* SDAM */
		psdmr |= ((tmp - 3 - 12) << 21);	/* BSMA */

		tmp = (31 - lsb - 10) - tmp;
		/* Pin connected to SDA10 is (31 - lsb - 10).
		   rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
		   so (rowst + tmp) alternates with AP.
		 */
		if (pbi)				/* Table 10-7 */
			psdmr |= ((10 - (rowst + tmp)) << 18);	/* SDA10 */
		else
			psdmr |= ((12 - (rowst + tmp)) << 18);	/* SDA10 */

		/* SDRAM device-specific parameters */
		tmp = ns2clk (70);	/* Refresh recovery is not in SPD, so assume 70ns */
		switch (tmp) {		/* RFRC */
		case 1:
		case 2:
			psdmr |= (1 << 15);
			break;
		case 3:
		case 4:
		case 5:
		case 6:
		case 7:
		case 8:
			psdmr |= ((tmp - 2) << 15);
			break;
		default:
			psdmr |= (7 << 15);
		}
		psdmr |= (ns2clk (spd.trp) % 8 << 12);	/* PRETOACT */
		psdmr |= (ns2clk (spd.trcd) % 8 << 9);	/* ACTTORW */
		/* BL=0 because for 64-bit SDRAM burst length must be 4 */
		/* LDOTOPRE ??? */
		for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
			tmp >>= 1;
		switch (i) {			/* WRC */
		case 0:
		case 1:
			psdmr |= (1 << 4);
			break;
		case 2:
		case 3:
			psdmr |= (i << 4);
			break;
		}
		/* EAMUX=0 - no external address multiplexing */
		/* BUFCMD=0 - no external buffers */
		for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
			tmp >>= 1;
		psdmr |= i;				/* CL */

		switch (spd.refresh & 0x7F) {
		case 1:
			tmp = 3900;
			break;
		case 2:
			tmp = 7800;
			break;
		case 3:
			tmp = 31300;
			break;
		case 4:
			tmp = 62500;
			break;
		case 5:
			tmp = 125000;
			break;
		default:
			tmp = 15625;
		}
		psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
				  ((memctl->memc_mptpr >> 8) + 1)) - 1;
#ifdef SPD_DEBUG
		printf ("\nDIMM type:       %-18.18s\n", spd.mpart);
		printf ("SPD size:        %d\n", spd.info_size);
		printf ("EEPROM size:     %d\n", 1 << spd.chip_size);
		printf ("Memory type:     %d\n", spd.mem_type);
		printf ("Row addr:        %d\n", spd.nrow_addr);
		printf ("Column addr:     %d\n", spd.ncol_addr);
		printf ("# of rows:       %d\n", spd.nrows);
		printf ("Row density:     %d\n", spd.row_dens);
		printf ("# of banks:      %d\n", spd.nbanks);
		printf ("Data width:      %d\n",
				256 * spd.dataw_msb + spd.dataw_lsb);
		printf ("Chip width:      %d\n", spd.primw);
		printf ("Refresh rate:    %02X\n", spd.refresh);
		printf ("CAS latencies:   %02X\n", spd.cas_lat);
		printf ("Write latencies: %02X\n", spd.write_lat);
		printf ("tRP:             %d\n", spd.trp);
		printf ("tRCD:            %d\n", spd.trcd);

		printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
#endif /* SPD_DEBUG */
	}
#endif /* CONFIG_SPD_EEPROM */
	memctl->memc_psrt = psrt;
	memctl->memc_or2 = or;
	memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
	ramaddr = (uchar *) CFG_SDRAM_BASE;
	memctl->memc_psdmr = psdmr | 0x28000000;	/* Precharge all banks */
	*ramaddr = c;
	memctl->memc_psdmr = psdmr | 0x08000000;	/* CBR refresh */
	for (i = 0; i < 8; i++)
		*ramaddr = c;

	memctl->memc_psdmr = psdmr | 0x18000000;	/* Mode Register write */
	*ramaddr = c;
	memctl->memc_psdmr = psdmr | 0x40000000;	/* Refresh enable */
	*ramaddr = c;
#endif

	/* return total ram size of DIMM */
	return (msize * 1024 * 1024);
}

int checkboard (void)
{
	puts ("Board: Motorola MPC8260ADS\n");
	return 0;
}
Commit	Line	Data
67c4f48a	1	/*
db2f721f	2	* (C) Copyright 2001-2003
67c4f48a WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* Modified during 2001 by
	6	* Advanced Communications Technologies (Australia) Pty. Ltd.
	7	* Howard Walker, Tuong Vu-Dinh
	8	*
	9	* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
	10	* Added support for the 16M dram simm on the 8260ads boards
	11	*
48b42616 WD	12	* (C) Copyright 2003 Arabella Software Ltd.
	13	* Yuli Barcohen <yuli@arabellasw.com>
	14	* Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
	15	*
67c4f48a WD	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	*/
	34
	35	#include <common.h>
	36	#include <ioports.h>
	37	#include <mpc8260.h>
db2f721f WD	38	#include <i2c.h>
db2f721f WD	39	#include <spd.h>
67c4f48a WD	40
	41	/*
	42	* I/O Port configuration table
	43	*
	44	* if conf is 1, then that port pin will be configured at boot time
	45	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	46	*/
	47
	48	const iop_conf_t iop_conf_tab[4][32] = {
	49
	50	/* Port A configuration */
	51	{ /* conf ppar psor pdir podr pdat */
	52	/* PA31 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxENB */
	53	/* PA30 / { 0, 1, 0, 0, 0, 0 }, / FCC1 TxClav */
	54	/* PA29 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxSOC */
	55	/* PA28 / { 0, 1, 0, 1, 0, 0 }, / FCC1 RxENB */
	56	/* PA27 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxSOC */
	57	/* PA26 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxClav */
	58	/* PA25 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[0] */
	59	/* PA24 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[1] */
	60	/* PA23 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[2] */
	61	/* PA22 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[3] */
	62	/* PA21 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[4] */
	63	/* PA20 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[5] */
	64	/* PA19 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[6] */
	65	/* PA18 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[7] */
	66	/* PA17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[7] */
	67	/* PA16 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[6] */
	68	/* PA15 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[5] */
	69	/* PA14 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[4] */
	70	/* PA13 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[3] */
	71	/* PA12 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[2] */
	72	/* PA11 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[1] */
	73	/* PA10 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[0] */
	74	/* PA9 / { 0, 1, 1, 1, 0, 0 }, / FCC1 L1TXD */
	75	/* PA8 / { 0, 1, 1, 0, 0, 0 }, / FCC1 L1RXD */
	76	/* PA7 / { 0, 0, 0, 1, 0, 0 }, / PA7 */
	77	/* PA6 / { 1, 1, 1, 1, 0, 0 }, / TDM A1 L1RSYNC */
	78	/* PA5 / { 0, 0, 0, 1, 0, 0 }, / PA5 */
	79	/* PA4 / { 0, 0, 0, 1, 0, 0 }, / PA4 */
	80	/* PA3 / { 0, 0, 0, 1, 0, 0 }, / PA3 */
	81	/* PA2 / { 0, 0, 0, 1, 0, 0 }, / PA2 */
	82	/* PA1 / { 1, 0, 0, 0, 0, 0 }, / FREERUN */
	83	/* PA0 / { 0, 0, 0, 1, 0, 0 } / PA0 */
	84	},
	85
	86	/* Port B configuration */
	87	{ /* conf ppar psor pdir podr pdat */
	88	/* PB31 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
	89	/* PB30 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
	90	/* PB29 / { 1, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
	91	/* PB28 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
	92	/* PB27 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
	93	/* PB26 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
	94	/* PB25 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
	95	/* PB24 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
	96	/* PB23 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
	97	/* PB22 / { 1, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
	98	/* PB21 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
	99	/* PB20 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
	100	/* PB19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
	101	/* PB18 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
	102	/* PB17 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_DIV */
	103	/* PB16 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RX_ERR */
104	/* PB15 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_ERR */
105	/* PB14 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TX_EN */
106	/* PB13 / { 0, 1, 0, 0, 0, 0 }, / FCC3:COL */
107	/* PB12 / { 0, 1, 0, 0, 0, 0 }, / FCC3:CRS */
108	/* PB11 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
109	/* PB10 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
110	/* PB9 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
111	/* PB8 / { 0, 1, 0, 0, 0, 0 }, / FCC3:RXD */
112	/* PB7 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
113	/* PB6 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
114	/* PB5 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
115	/* PB4 / { 0, 1, 0, 1, 0, 0 }, / FCC3:TXD */
116	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
117	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
118	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
119	/* PB0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
120	},
121
122	/* Port C */
123	{ /* conf ppar psor pdir podr pdat */
124	/* PC31 / { 0, 0, 0, 1, 0, 0 }, / PC31 */
125	/* PC30 / { 0, 0, 0, 1, 0, 0 }, / PC30 */
126	/* PC29 / { 0, 1, 1, 0, 0, 0 }, / SCC1 EN CLSN /
127	/* PC28 / { 0, 0, 0, 1, 0, 0 }, / PC28 */
128	/* PC27 / { 0, 0, 0, 1, 0, 0 }, / UART Clock in */
129	/* PC26 / { 0, 0, 0, 1, 0, 0 }, / PC26 */
130	/* PC25 / { 0, 0, 0, 1, 0, 0 }, / PC25 */
131	/* PC24 / { 0, 0, 0, 1, 0, 0 }, / PC24 */
132	/* PC23 / { 0, 1, 0, 1, 0, 0 }, / ATMTFCLK */
133	/* PC22 / { 0, 1, 0, 0, 0, 0 }, / ATMRFCLK */
134	/* PC21 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN RXCLK */
135	/* PC20 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN TXCLK */
136	/* PC19 / { 1, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK CLK13 */
137	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK14) */
138	/* PC17 / { 0, 0, 0, 1, 0, 0 }, / PC17 */
139	/* PC16 / { 0, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK16) */
140	/* PC15 / { 0, 0, 0, 1, 0, 0 }, / PC15 */
141	/* PC14 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CD /
142	/* PC13 / { 0, 0, 0, 1, 0, 0 }, / PC13 */
143	/* PC12 / { 0, 1, 0, 1, 0, 0 }, / PC12 */
144	/* PC11 / { 0, 0, 0, 1, 0, 0 }, / LXT971 transmit control */
145	/* PC10 / { 1, 1, 0, 0, 0, 0 }, / LXT970 FETHMDC */
146	/* PC9 / { 1, 1, 0, 0, 0, 0 }, / LXT970 FETHMDIO */
147	/* PC8 / { 0, 0, 0, 1, 0, 0 }, / PC8 */
148	/* PC7 / { 0, 0, 0, 1, 0, 0 }, / PC7 */
149	/* PC6 / { 0, 0, 0, 1, 0, 0 }, / PC6 */
150	/* PC5 / { 0, 0, 0, 1, 0, 0 }, / PC5 */
151	/* PC4 / { 0, 0, 0, 1, 0, 0 }, / PC4 */
152	/* PC3 / { 0, 0, 0, 1, 0, 0 }, / PC3 */
153	/* PC2 / { 0, 0, 0, 1, 0, 1 }, / ENET FDE */
154	/* PC1 / { 0, 0, 0, 1, 0, 0 }, / ENET DSQE */
155	/* PC0 / { 0, 0, 0, 1, 0, 0 }, / ENET LBK */
156	},
157
158	/* Port D */
159	{ /* conf ppar psor pdir podr pdat */
160	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN RxD */
161	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 EN TxD */
162	/* PD29 / { 0, 1, 0, 1, 0, 0 }, / SCC1 EN TENA */
163	/* PD28 / { 0, 1, 0, 0, 0, 0 }, / PD28 */
164	/* PD27 / { 0, 1, 1, 1, 0, 0 }, / PD27 */
165	/* PD26 / { 0, 0, 0, 1, 0, 0 }, / PD26 */
166	/* PD25 / { 0, 0, 0, 1, 0, 0 }, / PD25 */
167	/* PD24 / { 0, 0, 0, 1, 0, 0 }, / PD24 */
168	/* PD23 / { 0, 0, 0, 1, 0, 0 }, / PD23 */
169	/* PD22 / { 0, 0, 0, 1, 0, 0 }, / PD22 */
170	/* PD21 / { 0, 0, 0, 1, 0, 0 }, / PD21 */
171	/* PD20 / { 0, 0, 0, 1, 0, 0 }, / PD20 */
172	/* PD19 / { 0, 0, 0, 1, 0, 0 }, / PD19 */
173	/* PD18 / { 0, 0, 0, 1, 0, 0 }, / PD18 */
174	/* PD17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXPRTY */
175	/* PD16 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXPRTY */
db2f721f WD	176	/* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA */
db2f721f WD	177	/* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL */
67c4f48a WD	178	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
	179	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
	180	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
	181	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
	182	/* PD9 / { 1, 1, 0, 1, 0, 0 }, / SMC1 TXD */
	183	/* PD8 / { 1, 1, 0, 0, 0, 0 }, / SMC1 RXD */
	184	/* PD7 / { 0, 0, 0, 1, 0, 1 }, / PD7 */
	185	/* PD6 / { 0, 0, 0, 1, 0, 1 }, / PD6 */
	186	/* PD5 / { 0, 0, 0, 1, 0, 1 }, / PD5 */
	187	/* PD4 / { 0, 0, 0, 1, 0, 1 }, / PD4 */
	188	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	189	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	190	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
	191	/* PD0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
	192	}
	193	};
	194
	195	typedef struct bscr_ {
	196	unsigned long bcsr0;
	197	unsigned long bcsr1;
	198	unsigned long bcsr2;
	199	unsigned long bcsr3;
	200	unsigned long bcsr4;
	201	unsigned long bcsr5;
	202	unsigned long bcsr6;
	203	unsigned long bcsr7;
	204	} bcsr_t;
	205
db2f721f	206	void reset_phy (void)
67c4f48a	207	{
db2f721f	208	volatile bcsr_t bcsr = (bcsr_t ) CFG_BCSR;
67c4f48a	209
db2f721f WD	210	/* reset the FEC port */
	211	bcsr->bcsr1 &= ~FETH_RST;
	212	bcsr->bcsr1 \|= FETH_RST;
67c4f48a WD	213	}
	214
	215
	216	int board_pre_init (void)
	217	{
db2f721f	218	volatile bcsr_t bcsr = (bcsr_t ) CFG_BCSR;
67c4f48a	219
db2f721f WD	220	bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;
	221
	222	return 0;
67c4f48a WD	223	}
67c4f48a WD	224
db2f721f WD	225	#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
	226
	227	long int initdram (int board_type)
67c4f48a	228	{
db2f721f WD	229	volatile immap_t immap = (immap_t ) CFG_IMMR;
	230	volatile memctl8260_t *memctl = &immap->im_memctl;
	231	volatile uchar *ramaddr, c = 0xff;
	232
	233	/* Initialisation is for 16MB DIMM the board is shipped with */
	234	long int msize = 16;
	235	uint or = 0xFF000CA0;
	236	uint psdmr = CFG_PSDMR;
	237	uint psrt = CFG_PSRT;
	238
	239	int i;
67c4f48a WD	240
67c4f48a WD	241	#ifndef CFG_RAMBOOT
db2f721f WD	242	immap->im_siu_conf.sc_ppc_acr = 0x00000002;
	243	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
	244	immap->im_siu_conf.sc_tescr1 = 0x00004000;
	245
	246	memctl->memc_mptpr = CFG_MPTPR;
	247	/* init local sdram, bank 4 */
	248	memctl->memc_lsrt = 0x00000010;
	249	memctl->memc_or4 = 0xFFC01480;
	250	memctl->memc_br4 = 0x04001861;
	251	memctl->memc_lsdmr = 0x2886A522;
	252	ramaddr = (uchar *) CFG_LSDRAM_BASE;
	253	*ramaddr = c;
	254	memctl->memc_lsdmr = 0x0886A522;
	255	for (i = 0; i < 8; i++) {
	256	*ramaddr = c;
	257	}
	258	memctl->memc_lsdmr = 0x1886A522;
	259	*ramaddr = c;
	260	memctl->memc_lsdmr = 0x4086A522;
	261
	262	/* init sdram dimm */
	263	#ifdef CONFIG_SPD_EEPROM
	264	{
	265	spd_eeprom_t spd;
	266	uint pbi, bsel, rowst, lsb, tmp;
	267
	268	i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
	269
	270	/* Bank-based interleaving is not supported for physical bank
	271	sizes greater than 128MB which is encoded as 0x20 in SPD
	272	*/
	273	pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
	274	msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
	275	or = ~(msize - 1) << 20; /* SDAM */
	276	switch (spd.nbanks) { /* BPD */
	277	case 2:
	278	bsel = 1;
	279	break;
	280	case 4:
	281	bsel = 2;
	282	or \|= 0x00002000;
	283	break;
	284	case 8:
	285	bsel = 3;
	286	or \|= 0x00004000;
	287	break;
	288	}
	289	lsb = 3; /* For 64-bit port, lsb is 3 bits */
	290
	291	if (pbi) { /* Bus partition depends on interleaving */
	292	rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
	293	or \|= (rowst << 9); /* ROWST */
	294	} else {
	295	rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
	296	or \|= ((rowst * 2 - 12) << 9); /* ROWST */
	297	}
	298	or \|= ((spd.nrow_addr - 9) << 6); /* NUMR */
	299
	300	psdmr = (pbi << 31); /* PBI */
	301	/* Bus multiplexing parameters */
	302	tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
	303	psdmr \|= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
	304	psdmr \|= ((tmp - 3 - 12) << 21); /* BSMA */
	305
306	tmp = (31 - lsb - 10) - tmp;
307	/* Pin connected to SDA10 is (31 - lsb - 10).
308	rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
309	so (rowst + tmp) alternates with AP.
310	*/
311	if (pbi) /* Table 10-7 */
312	psdmr \|= ((10 - (rowst + tmp)) << 18); /* SDA10 */
313	else
314	psdmr \|= ((12 - (rowst + tmp)) << 18); /* SDA10 */
315
316	/* SDRAM device-specific parameters */
317	tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
318	switch (tmp) { /* RFRC */
319	case 1:
320	case 2:
321	psdmr \|= (1 << 15);
322	break;
323	case 3:
324	case 4:
325	case 5:
326	case 6:
327	case 7:
328	case 8:
329	psdmr \|= ((tmp - 2) << 15);
330	break;
331	default:
332	psdmr \|= (7 << 15);
333	}
334	psdmr \|= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
335	psdmr \|= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
336	/* BL=0 because for 64-bit SDRAM burst length must be 4 */
337	/* LDOTOPRE ??? */
338	for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
339	tmp >>= 1;
340	switch (i) { /* WRC */
341	case 0:
342	case 1:
343	psdmr \|= (1 << 4);
344	break;
345	case 2:
346	case 3:
347	psdmr \|= (i << 4);
348	break;
349	}
350	/* EAMUX=0 - no external address multiplexing */
351	/* BUFCMD=0 - no external buffers */
352	for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
353	tmp >>= 1;
354	psdmr \|= i; /* CL */
355
356	switch (spd.refresh & 0x7F) {
357	case 1:
358	tmp = 3900;
359	break;
360	case 2:
361	tmp = 7800;
362	break;
363	case 3:
364	tmp = 31300;
365	break;
366	case 4:
367	tmp = 62500;
368	break;
369	case 5:
370	tmp = 125000;
371	break;
372	default:
373	tmp = 15625;
374	}
375	psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
376	((memctl->memc_mptpr >> 8) + 1)) - 1;
377	#ifdef SPD_DEBUG
378	printf ("\nDIMM type: %-18.18s\n", spd.mpart);
379	printf ("SPD size: %d\n", spd.info_size);
380	printf ("EEPROM size: %d\n", 1 << spd.chip_size);
381	printf ("Memory type: %d\n", spd.mem_type);
382	printf ("Row addr: %d\n", spd.nrow_addr);
383	printf ("Column addr: %d\n", spd.ncol_addr);
384	printf ("# of rows: %d\n", spd.nrows);
385	printf ("Row density: %d\n", spd.row_dens);
386	printf ("# of banks: %d\n", spd.nbanks);
387	printf ("Data width: %d\n",
388	256 * spd.dataw_msb + spd.dataw_lsb);
389	printf ("Chip width: %d\n", spd.primw);
390	printf ("Refresh rate: %02X\n", spd.refresh);
391	printf ("CAS latencies: %02X\n", spd.cas_lat);
392	printf ("Write latencies: %02X\n", spd.write_lat);
393	printf ("tRP: %d\n", spd.trp);
394	printf ("tRCD: %d\n", spd.trcd);
395
396	printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
397	#endif /* SPD_DEBUG */
398	}
399	#endif /* CONFIG_SPD_EEPROM */
400	memctl->memc_psrt = psrt;
401	memctl->memc_or2 = or;
402	memctl->memc_br2 = CFG_SDRAM_BASE \| 0x00000041;
403	ramaddr = (uchar *) CFG_SDRAM_BASE;
404	memctl->memc_psdmr = psdmr \| 0x28000000; /* Precharge all banks */
405	*ramaddr = c;
406	memctl->memc_psdmr = psdmr \| 0x08000000; /* CBR refresh */
407	for (i = 0; i < 8; i++)
408	*ramaddr = c;
409
410	memctl->memc_psdmr = psdmr \| 0x18000000; /* Mode Register write */
411	*ramaddr = c;
412	memctl->memc_psdmr = psdmr \| 0x40000000; /* Refresh enable */
413	*ramaddr = c;
67c4f48a WD	414	#endif
67c4f48a WD	415
db2f721f WD	416	/* return total ram size of DIMM */
db2f721f WD	417	return (msize * 1024 * 1024);
67c4f48a WD	418	}
67c4f48a WD	419
db2f721f	420	int checkboard (void)
67c4f48a	421	{
db2f721f WD	422	puts ("Board: Motorola MPC8260ADS\n");
db2f721f WD	423	return 0;
67c4f48a	424	}