[people/ms/u-boot.git] / board / mpc8349ads / mpc8349ads.c

/*
 * Copyright Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * Change log:
 * 20050101: Eran Liberty (liberty@freescale.com)
 *           Initial file creating (porting from 85XX & 8260)
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
int fixed_sdram(void);
void sdram_init(void);

int board_early_init_f (void)
{
	volatile u8* bcsr = (volatile u8*)CFG_BCSR;

	/* Enable flash write */
	bcsr[1] &= ~0x01;

	return 0;
}


#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)

long int initdram (int board_type)
{
	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram(NULL);
#else
	msize = fixed_sdram();
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();
	puts("   DDR RAM: ");
	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}


#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
	u32 msize = 0;
	u32 ddr_size;
	u32 ddr_size_log2;

	msize = CFG_DDR_SIZE;
	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	     (ddr_size > 1);
	     ddr_size = ddr_size>>1, ddr_size_log2++) {
		if (ddr_size & 1) {
			return -1;
		}
	}
	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CFG_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif

	im->ddr.csbnds[0].csbnds = 0x00100017;
	im->ddr.csbnds[1].csbnds = 0x0018001f;
	im->ddr.csbnds[2].csbnds = 0x00000007;
	im->ddr.csbnds[3].csbnds = 0x0008000f;
	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
	im->ddr.cs_config[1] = CFG_DDR_CONFIG;
	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
	im->ddr.cs_config[3] = CFG_DDR_CONFIG;
	im->ddr.timing_cfg_1 =
		3 << TIMING_CFG1_PRETOACT_SHIFT |
		7 << TIMING_CFG1_ACTTOPRE_SHIFT |
		3 << TIMING_CFG1_ACTTORW_SHIFT  |
		4 << TIMING_CFG1_CASLAT_SHIFT   |
		3 << TIMING_CFG1_REFREC_SHIFT   |
		3 << TIMING_CFG1_WRREC_SHIFT    |
		2 << TIMING_CFG1_ACTTOACT_SHIFT |
		1 << TIMING_CFG1_WRTORD_SHIFT;
	im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
	im->ddr.sdram_cfg =
		SDRAM_CFG_SREN
#if defined(CONFIG_DDR_2T_TIMING)
		| SDRAM_CFG_2T_EN
#endif
		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
	im->ddr.sdram_mode =
		0x2000 << SDRAM_MODE_ESD_SHIFT |
		0x0162 << SDRAM_MODE_SD_SHIFT;

	im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
		0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
	udelay(200);

	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;

	return msize;
}
#endif/*!CFG_SPD_EEPROM*/


int checkboard (void)
{
	puts("Board: Freescale MPC8349ADS\n");
	return 0;
}

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found
 */
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc83xxads_config_table[] = {
	{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				    PCI_ENET0_MEMADDR,
				    PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
	} },
	{}
}
#endif


volatile static struct pci_controller hose[] = {
	{
#ifndef CONFIG_PCI_PNP
	config_table:pci_mpc83xxads_config_table,
#endif
	},
	{
#ifndef CONFIG_PCI_PNP
	config_table:pci_mpc83xxads_config_table,
#endif
	}
};
#endif /* CONFIG_PCI */


void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	extern void pci_mpc83xx_init(volatile struct pci_controller *hose);

	pci_mpc83xx_init(hose);
#endif /* CONFIG_PCI */
}

/*
 * if MPC8349ADS is soldered with SDRAM
 */
#if defined(CFG_BR2_PRELIM)  \
	&& defined(CFG_OR2_PRELIM) \
	&& defined(CFG_LBLAWBAR2_PRELIM) \
	&& defined(CFG_LBLAWAR2_PRELIM)
/*
 * Initialize SDRAM memory on the Local Bus.
 */

void
sdram_init(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
	volatile lbus8349_t *lbc= &immap->lbus;
	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;

	puts("\n   SDRAM on Local Bus: ");
	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
	 */

	/*setup mtrpt, lsrt and lbcr for LB bus*/
	lbc->lbcr = CFG_LBC_LBCR;
	lbc->mrtpr = CFG_LBC_MRTPR;
	lbc->lsrt = CFG_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/

	lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
	asm("sync");
	/*1 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*2 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*3 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*4 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*5 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*6 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*7 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*8 times*/
	*sdram_addr = 0xff;
	udelay(100);

	/* 0x58636733;mode register write operation */
	lbc->lsdmr = CFG_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);
}
#else
void
sdram_init(void)
{
	put("SDRAM on Local Bus is NOT available!\n");
}
#endif
Commit	Line	Data
f046ccd1 EL	1	/*
	2	* Copyright Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*
	22	* Change log:
	23	* 20050101: Eran Liberty (liberty@freescale.com)
	24	* Initial file creating (porting from 85XX & 8260)
	25	*/
	26
	27	#include <common.h>
	28	#include <ioports.h>
	29	#include <mpc83xx.h>
	30	#include <asm/mpc8349_pci.h>
	31	#include <i2c.h>
	32	#include <spd.h>
	33	#include <miiphy.h>
	34	#if defined(CONFIG_PCI)
	35	#include <pci.h>
	36	#endif
	37	#if defined(CONFIG_SPD_EEPROM)
	38	#include <spd_sdram.h>
	39	#endif
	40	int fixed_sdram(void);
	41	void sdram_init(void);
	42
	43	int board_early_init_f (void)
	44	{
	45	volatile u8* bcsr = (volatile u8*)CFG_BCSR;
	46
	47	/* Enable flash write */
	48	bcsr[1] &= ~0x01;
	49
	50	return 0;
	51	}
	52
	53
	54	#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
	55
f046ccd1 EL	56	long int initdram (int board_type)
	57	{
	58	volatile immap_t im = (immap_t )CFG_IMMRBAR;
	59	u32 msize = 0;
	60
	61	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
	62	return -1;
	63
	64	/* DDR SDRAM - Main SODIMM */
	65	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
	66	#if defined(CONFIG_SPD_EEPROM)
	67	msize = spd_sdram(NULL);
	68	#else
	69	msize = fixed_sdram();
	70	#endif
	71	/*
	72	* Initialize SDRAM if it is on local bus.
	73	*/
	74	sdram_init();
	75	puts(" DDR RAM: ");
	76	/* return total bus SDRAM size(bytes) -- DDR */
	77	return (msize * 1024 * 1024);
	78	}
	79
	80
	81	#if !defined(CONFIG_SPD_EEPROM)
	82	/*************************************************************************
	83	* fixed sdram init -- doesn't use serial presence detect.
	84	************************************************************************/
	85	int fixed_sdram(void)
	86	{
	87	volatile immap_t im = (immap_t )CFG_IMMRBAR;
	88	u32 msize = 0;
	89	u32 ddr_size;
	90	u32 ddr_size_log2;
	91
	92	msize = CFG_DDR_SIZE;
	93	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	94	(ddr_size > 1);
	95	ddr_size = ddr_size>>1, ddr_size_log2++) {
	96	if (ddr_size & 1) {
	97	return -1;
	98	}
	99	}
	100	im->sysconf.ddrlaw[0].ar = LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
	101	#if (CFG_DDR_SIZE != 256)
	102	#warning Currenly any ddr size other than 256 is not supported
	103	#endif
	104
	105	im->ddr.csbnds[0].csbnds = 0x00100017;
	106	im->ddr.csbnds[1].csbnds = 0x0018001f;
	107	im->ddr.csbnds[2].csbnds = 0x00000007;
	108	im->ddr.csbnds[3].csbnds = 0x0008000f;
	109	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
	110	im->ddr.cs_config[1] = CFG_DDR_CONFIG;
	111	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
	112	im->ddr.cs_config[3] = CFG_DDR_CONFIG;
	113	im->ddr.timing_cfg_1 =
	114	3 << TIMING_CFG1_PRETOACT_SHIFT \|
	115	7 << TIMING_CFG1_ACTTOPRE_SHIFT \|
	116	3 << TIMING_CFG1_ACTTORW_SHIFT \|
	117	4 << TIMING_CFG1_CASLAT_SHIFT \|
	118	3 << TIMING_CFG1_REFREC_SHIFT \|
	119	3 << TIMING_CFG1_WRREC_SHIFT \|
120	2 << TIMING_CFG1_ACTTOACT_SHIFT \|
121	1 << TIMING_CFG1_WRTORD_SHIFT;
122	im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
123	im->ddr.sdram_cfg =
124	SDRAM_CFG_SREN
125	#if defined(CONFIG_DDR_2T_TIMING)
126	\| SDRAM_CFG_2T_EN
127	#endif
128	\| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
129	im->ddr.sdram_mode =
130	0x2000 << SDRAM_MODE_ESD_SHIFT \|
131	0x0162 << SDRAM_MODE_SD_SHIFT;
132
133	im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT \|
134	0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
135	udelay(200);
136
137	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
138
139	return msize;
140	}
141	#endif/!CFG_SPD_EEPROM/
142
143
144	int checkboard (void)
145	{
146	puts("Board: Freescale MPC8349ADS\n");
147	return 0;
148	}
149
de1d0a69	150	#if defined(CONFIG_PCI)
f046ccd1 EL	151	/*
	152	* Initialize PCI Devices, report devices found
	153	*/
	154	#ifndef CONFIG_PCI_PNP
	155	static struct pci_config_table pci_mpc83xxads_config_table[] = {
	156	{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
	157	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	158	PCI_ENET0_MEMADDR,
	159	PCI_COMMON_MEMORY \| PCI_COMMAND_MASTER
	160	} },
	161	{}
	162	}
	163	#endif
	164
	165
	166	volatile static struct pci_controller hose[] = {
	167	{
	168	#ifndef CONFIG_PCI_PNP
	169	config_table:pci_mpc83xxads_config_table,
	170	#endif
	171	},
	172	{
	173	#ifndef CONFIG_PCI_PNP
	174	config_table:pci_mpc83xxads_config_table,
	175	#endif
	176	}
	177	};
	178	#endif /* CONFIG_PCI */
	179
	180
	181	void
	182	pci_init_board(void)
	183	{
	184	#ifdef CONFIG_PCI
	185	extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
	186
	187	pci_mpc83xx_init(hose);
	188	#endif /* CONFIG_PCI */
	189	}
	190
	191	/*
de1d0a69 JL	192	* if MPC8349ADS is soldered with SDRAM
de1d0a69 JL	193	*/
f046ccd1 EL	194	#if defined(CFG_BR2_PRELIM) \
	195	&& defined(CFG_OR2_PRELIM) \
	196	&& defined(CFG_LBLAWBAR2_PRELIM) \
	197	&& defined(CFG_LBLAWAR2_PRELIM)
	198	/*
	199	* Initialize SDRAM memory on the Local Bus.
	200	*/
	201
	202	void
	203	sdram_init(void)
	204	{
	205	volatile immap_t immap = (immap_t )CFG_IMMRBAR;
	206	volatile lbus8349_t *lbc= &immap->lbus;
	207	uint sdram_addr = (uint )CFG_LBC_SDRAM_BASE;
	208
f046ccd1 EL	209	puts("\n SDRAM on Local Bus: ");
	210	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
	211
	212	/*
	213	* Setup SDRAM Base and Option Registers, already done in cpu_init.c
	214	*/
	215
	216	/setup mtrpt, lsrt and lbcr for LB bus/
	217	lbc->lbcr = CFG_LBC_LBCR;
	218	lbc->mrtpr = CFG_LBC_MRTPR;
	219	lbc->lsrt = CFG_LBC_LSRT;
	220	asm("sync");
	221
	222	/*
	223	* Configure the SDRAM controller Machine Mode Register.
	224	*/
	225	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/
	226
	227	lbc->lsdmr = CFG_LBC_LSDMR_1; /0x68636733;precharge all the banks/
	228	asm("sync");
	229	*sdram_addr = 0xff;
	230	udelay(100);
	231
	232	lbc->lsdmr = CFG_LBC_LSDMR_2;/0x48636733;auto refresh/
	233	asm("sync");
de1d0a69	234	/1 times/
f046ccd1 EL	235	*sdram_addr = 0xff;
f046ccd1 EL	236	udelay(100);
de1d0a69	237	/2 times/
f046ccd1 EL	238	*sdram_addr = 0xff;
f046ccd1 EL	239	udelay(100);
de1d0a69	240	/3 times/
f046ccd1 EL	241	*sdram_addr = 0xff;
f046ccd1 EL	242	udelay(100);
de1d0a69	243	/4 times/
f046ccd1 EL	244	*sdram_addr = 0xff;
f046ccd1 EL	245	udelay(100);
de1d0a69	246	/5 times/
f046ccd1 EL	247	*sdram_addr = 0xff;
f046ccd1 EL	248	udelay(100);
de1d0a69	249	/6 times/
f046ccd1 EL	250	*sdram_addr = 0xff;
f046ccd1 EL	251	udelay(100);
de1d0a69	252	/7 times/
f046ccd1 EL	253	*sdram_addr = 0xff;
f046ccd1 EL	254	udelay(100);
de1d0a69	255	/8 times/
f046ccd1 EL	256	*sdram_addr = 0xff;
	257	udelay(100);
	258
de1d0a69 JL	259	/* 0x58636733;mode register write operation */
de1d0a69 JL	260	lbc->lsdmr = CFG_LBC_LSDMR_4;
f046ccd1 EL	261	asm("sync");
	262	*sdram_addr = 0xff;
	263	udelay(100);
	264
	265	lbc->lsdmr = CFG_LBC_LSDMR_5; /0x40636733;normal operation/
	266	asm("sync");
	267	*sdram_addr = 0xff;
	268	udelay(100);
	269	}
	270	#else
	271	void
	272	sdram_init(void)
	273	{
	274	put("SDRAM on Local Bus is NOT available!\n");
	275	}
	276	#endif