[people/ms/u-boot.git] / board / mpc8349emds / mpc8349emds.c

/*
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#include <command.h>
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif

int fixed_sdram(void);
void sdram_init(void);

#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
void ddr_enable_ecc(unsigned int dram_size);
#endif

int board_early_init_f (void)
{
	volatile u8* bcsr = (volatile u8*)CFG_BCSR;

	/* Enable flash write */
	bcsr[1] &= ~0x01;

#ifdef CFG_USE_MPC834XSYS_USB_PHY
	/* Use USB PHY on SYS board */
	bcsr[5] |= 0x02;
#endif

	return 0;
}

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)

long int initdram (int board_type)
{
	volatile immap_t *im = (immap_t *)CFG_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
		return -1;

	puts("Initializing\n");

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	puts("   DDR RAM: ");
	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *)CFG_IMMR;
	u32 msize = 0;
	u32 ddr_size;
	u32 ddr_size_log2;

	msize = CFG_DDR_SIZE;
	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	     (ddr_size > 1);
	     ddr_size = ddr_size>>1, ddr_size_log2++) {
		if (ddr_size & 1) {
			return -1;
		}
	}
	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);

#if (CFG_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
	im->ddr.csbnds[2].csbnds = 0x0000000f;
	im->ddr.cs_config[2] = CFG_DDR_CONFIG;

	/* currently we use only one CS, so disable the other banks */
	im->ddr.cs_config[0] = 0;
	im->ddr.cs_config[1] = 0;
	im->ddr.cs_config[3] = 0;

	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;

	im->ddr.sdram_cfg =
		SDRAM_CFG_SREN
#if defined(CONFIG_DDR_2T_TIMING)
		| SDRAM_CFG_2T_EN
#endif
		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
#if defined (CONFIG_DDR_32BIT)
	/* for 32-bit mode burst length is 8 */
	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
#endif
	im->ddr.sdram_mode = CFG_DDR_MODE;

	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
	udelay(200);

	/* enable DDR controller */
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	return msize;
}
#endif/*!CFG_SPD_EEPROM*/


int checkboard (void)
{
	puts("Board: Freescale MPC8349EMDS\n");
	return 0;
}

/*
 * if MPC8349EMDS is soldered with SDRAM
 */
#if defined(CFG_BR2_PRELIM)  \
	&& defined(CFG_OR2_PRELIM) \
	&& defined(CFG_LBLAWBAR2_PRELIM) \
	&& defined(CFG_LBLAWAR2_PRELIM)
/*
 * Initialize SDRAM memory on the Local Bus.
 */

void sdram_init(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile lbus83xx_t *lbc= &immap->lbus;
	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;

	puts("\n   SDRAM on Local Bus: ");
	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
	 */

	/* setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CFG_LBC_LBCR;
	lbc->mrtpr = CFG_LBC_MRTPR;
	lbc->lsrt = CFG_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */

	lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
	asm("sync");
	/*1 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*2 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*3 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*4 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*5 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*6 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*7 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*8 times*/
	*sdram_addr = 0xff;
	udelay(100);

	/* 0x58636733; mode register write operation */
	lbc->lsdmr = CFG_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);
}
#else
void sdram_init(void)
{
	put("SDRAM on Local Bus is NOT available!\n");
}
#endif

#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
/*
 * ECC user commands
 */
void ecc_print_status(void)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ddr83xx_t *ddr = &immap->ddr;

	printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");

	/* Interrupts */
	printf("Memory Error Interrupt Enable:\n");
	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
			(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
	printf("  Single-Bit Error Interrupt Enable: %d\n",
			(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
	printf("  Memory Select Error Interrupt Enable: %d\n\n",
			(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);

	/* Error disable */
	printf("Memory Error Disable:\n");
	printf("  Multiple-Bit Error Disable: %d\n",
			(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
	printf("  Sinle-Bit Error Disable: %d\n",
			(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
	printf("  Memory Select Error Disable: %d\n\n",
			(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);

	/* Error injection */
	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
			ddr->data_err_inject_hi, ddr->data_err_inject_lo);

	printf("Memory Data Path Error Injection Mask ECC:\n");
	printf("  ECC Mirror Byte: %d\n",
			(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
	printf("  ECC Injection Enable: %d\n",
			(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
	printf("  ECC Error Injection Mask: 0x%02x\n\n",
			ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);

	/* SBE counter/threshold */
	printf("Memory Single-Bit Error Management (0..255):\n");
	printf("  Single-Bit Error Threshold: %d\n",
			(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
	printf("  Single-Bit Error Counter: %d\n\n",
			(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);

	/* Error detect */
	printf("Memory Error Detect:\n");
	printf("  Multiple Memory Errors: %d\n",
			(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
	printf("  Multiple-Bit Error: %d\n",
			(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
	printf("  Single-Bit Error: %d\n",
			(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
	printf("  Memory Select Error: %d\n\n",
			(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);

	/* Capture data */
	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
			ddr->capture_data_hi, ddr->capture_data_lo);
	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
		ddr->capture_ecc & CAPTURE_ECC_ECE);

	printf("Memory Error Attributes Capture:\n");
	printf("  Data Beat Number: %d\n",
			(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
	printf("  Transaction Size: %d\n",
			(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
	printf("  Transaction Source: %d\n",
			(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
	printf("  Transaction Type: %d\n",
			(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
	printf("  Error Information Valid: %d\n\n",
			ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
}

int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR;
	volatile ddr83xx_t *ddr = &immap->ddr;
	volatile u32 val;
	u64 *addr, count, val64;
	register u64 *i;

	if (argc > 4) {
		printf ("Usage:\n%s\n", cmdtp->usage);
		return 1;
	}

	if (argc == 2) {
		if (strcmp(argv[1], "status") == 0) {
			ecc_print_status();
			return 0;
		} else if (strcmp(argv[1], "captureclear") == 0) {
			ddr->capture_address = 0;
			ddr->capture_data_hi = 0;
			ddr->capture_data_lo = 0;
			ddr->capture_ecc = 0;
			ddr->capture_attributes = 0;
			return 0;
		}
	}

	if (argc == 3) {
		if (strcmp(argv[1], "sbecnt") == 0) {
			val = simple_strtoul(argv[2], NULL, 10);
			if (val > 255) {
				printf("Incorrect Counter value, should be 0..255\n");
				return 1;
			}

			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);

			ddr->err_sbe = val;
			return 0;
		} else if (strcmp(argv[1], "sbethr") == 0) {
			val = simple_strtoul(argv[2], NULL, 10);
			if (val > 255) {
				printf("Incorrect Counter value, should be 0..255\n");
				return 1;
			}

			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);

			ddr->err_sbe = val;
			return 0;
		} else if (strcmp(argv[1], "errdisable") == 0) {
			val = ddr->err_disable;

			if (strcmp(argv[2], "+sbe") == 0) {
				val |= ECC_ERROR_DISABLE_SBED;
			} else if (strcmp(argv[2], "+mbe") == 0) {
				val |= ECC_ERROR_DISABLE_MBED;
			} else if (strcmp(argv[2], "+mse") == 0) {
				val |= ECC_ERROR_DISABLE_MSED;
			} else if (strcmp(argv[2], "+all") == 0) {
				val |= (ECC_ERROR_DISABLE_SBED |
					ECC_ERROR_DISABLE_MBED |
					ECC_ERROR_DISABLE_MSED);
			} else if (strcmp(argv[2], "-sbe") == 0) {
				val &= ~ECC_ERROR_DISABLE_SBED;
			} else if (strcmp(argv[2], "-mbe") == 0) {
				val &= ~ECC_ERROR_DISABLE_MBED;
			} else if (strcmp(argv[2], "-mse") == 0) {
				val &= ~ECC_ERROR_DISABLE_MSED;
			} else if (strcmp(argv[2], "-all") == 0) {
				val &= ~(ECC_ERROR_DISABLE_SBED |
					ECC_ERROR_DISABLE_MBED |
					ECC_ERROR_DISABLE_MSED);
			} else {
				printf("Incorrect err_disable field\n");
				return 1;
			}

			ddr->err_disable = val;
			__asm__ __volatile__ ("sync");
			__asm__ __volatile__ ("isync");
			return 0;
		} else if (strcmp(argv[1], "errdetectclr") == 0) {
			val = ddr->err_detect;

			if (strcmp(argv[2], "mme") == 0) {
				val |= ECC_ERROR_DETECT_MME;
			} else if (strcmp(argv[2], "sbe") == 0) {
				val |= ECC_ERROR_DETECT_SBE;
			} else if (strcmp(argv[2], "mbe") == 0) {
				val |= ECC_ERROR_DETECT_MBE;
			} else if (strcmp(argv[2], "mse") == 0) {
				val |= ECC_ERROR_DETECT_MSE;
			} else if (strcmp(argv[2], "all") == 0) {
				val |= (ECC_ERROR_DETECT_MME |
					ECC_ERROR_DETECT_MBE |
					ECC_ERROR_DETECT_SBE |
					ECC_ERROR_DETECT_MSE);
			} else {
				printf("Incorrect err_detect field\n");
				return 1;
			}

			ddr->err_detect = val;
			return 0;
		} else if (strcmp(argv[1], "injectdatahi") == 0) {
			val = simple_strtoul(argv[2], NULL, 16);

			ddr->data_err_inject_hi = val;
			return 0;
		} else if (strcmp(argv[1], "injectdatalo") == 0) {
			val = simple_strtoul(argv[2], NULL, 16);

			ddr->data_err_inject_lo = val;
			return 0;
		} else if (strcmp(argv[1], "injectecc") == 0) {
			val = simple_strtoul(argv[2], NULL, 16);
			if (val > 0xff) {
				printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
				return 1;
			}
			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);

			ddr->ecc_err_inject = val;
			return 0;
		} else if (strcmp(argv[1], "inject") == 0) {
			val = ddr->ecc_err_inject;

			if (strcmp(argv[2], "en") == 0)
				val |= ECC_ERR_INJECT_EIEN;
			else if (strcmp(argv[2], "dis") == 0)
				val &= ~ECC_ERR_INJECT_EIEN;
			else
				printf("Incorrect command\n");

			ddr->ecc_err_inject = val;
			__asm__ __volatile__ ("sync");
			__asm__ __volatile__ ("isync");
			return 0;
		} else if (strcmp(argv[1], "mirror") == 0) {
			val = ddr->ecc_err_inject;

			if (strcmp(argv[2], "en") == 0)
				val |= ECC_ERR_INJECT_EMB;
			else if (strcmp(argv[2], "dis") == 0)
				val &= ~ECC_ERR_INJECT_EMB;
			else
				printf("Incorrect command\n");

			ddr->ecc_err_inject = val;
			return 0;
		}
	}

	if (argc == 4) {
		if (strcmp(argv[1], "test") == 0) {
			addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
			count = simple_strtoul(argv[3], NULL, 16);

			if ((u32)addr % 8) {
				printf("Address not alligned on double word boundary\n");
				return 1;
			}

			disable_interrupts();
			icache_disable();

			for (i = addr; i < addr + count; i++) {
				/* enable injects */
				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
				__asm__ __volatile__ ("sync");
				__asm__ __volatile__ ("isync");

				/* write memory location injecting errors */
				*i = 0x1122334455667788ULL;
				__asm__ __volatile__ ("sync");

				/* disable injects */
				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
				__asm__ __volatile__ ("sync");
				__asm__ __volatile__ ("isync");

				/* read data, this generates ECC error */
				val64 = *i;
				__asm__ __volatile__ ("sync");

				/* disable errors for ECC */
				ddr->err_disable |= ~ECC_ERROR_ENABLE;
				__asm__ __volatile__ ("sync");
				__asm__ __volatile__ ("isync");

				/* re-initialize memory, write the location again
				 * NOT injecting errors this time */
				*i = 0xcafecafecafecafeULL;
				__asm__ __volatile__ ("sync");

				/* enable errors for ECC */
				ddr->err_disable &= ECC_ERROR_ENABLE;
				__asm__ __volatile__ ("sync");
				__asm__ __volatile__ ("isync");
			}

			icache_enable();
			enable_interrupts();

			return 0;
		}
	}

	printf ("Usage:\n%s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	ecc,     4,     0,      do_ecc,
	"ecc     - support for DDR ECC features\n",
	"status              - print out status info\n"
	"ecc captureclear        - clear capture regs data\n"
	"ecc sbecnt <val>        - set Single-Bit Error counter\n"
	"ecc sbethr <val>        - set Single-Bit Threshold\n"
	"ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
	"  [-|+]sbe - Single-Bit Error\n"
	"  [-|+]mbe - Multiple-Bit Error\n"
	"  [-|+]mse - Memory Select Error\n"
	"  [-|+]all - all errors\n"
	"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
	"  mme - Multiple Memory Errors\n"
	"  sbe - Single-Bit Error\n"
	"  mbe - Multiple-Bit Error\n"
	"  mse - Memory Select Error\n"
	"  all - all errors\n"
	"ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
	"ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
	"ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
	"ecc inject <en|dis>    - enable/disable error injection\n"
	"ecc mirror <en|dis>    - enable/disable mirror byte\n"
	"ecc test <addr> <cnt>  - test mem region:\n"
	"  - enables injects\n"
	"  - writes pattern injecting errors\n"
	"  - disables injects\n"
	"  - reads pattern back, generates error\n"
	"  - re-inits memory"
);
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */

#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	u32 *p;
	int len;

#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
	ft_cpu_setup(blob, bd);

	p = ft_get_prop(blob, "/memory/reg", &len);
	if (p != NULL) {
		*p++ = cpu_to_be32(bd->bi_memstart);
		*p = cpu_to_be32(bd->bi_memsize);
	}
}
#endif
Commit	Line	Data
991425fe MB	1	/*
	2	* (C) Copyright 2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	#include <common.h>
	26	#include <ioports.h>
	27	#include <mpc83xx.h>
	28	#include <asm/mpc8349_pci.h>
	29	#include <i2c.h>
	30	#include <spd.h>
	31	#include <miiphy.h>
d326f4a2	32	#include <command.h>
991425fe MB	33	#if defined(CONFIG_SPD_EEPROM)
	34	#include <spd_sdram.h>
	35	#endif
bf0b542d KP	36	#if defined(CONFIG_OF_FLAT_TREE)
	37	#include <ft_build.h>
	38	#endif
	39
991425fe MB	40	int fixed_sdram(void);
	41	void sdram_init(void);
	42
	43	#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
	44	void ddr_enable_ecc(unsigned int dram_size);
	45	#endif
	46
	47	int board_early_init_f (void)
	48	{
	49	volatile u8* bcsr = (volatile u8*)CFG_BCSR;
	50
	51	/* Enable flash write */
	52	bcsr[1] &= ~0x01;
	53
8fe9bf61 KG	54	#ifdef CFG_USE_MPC834XSYS_USB_PHY
	55	/* Use USB PHY on SYS board */
	56	bcsr[5] \|= 0x02;
	57	#endif
	58
991425fe MB	59	return 0;
	60	}
	61
	62	#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
	63
	64	long int initdram (int board_type)
	65	{
d239d74b	66	volatile immap_t im = (immap_t )CFG_IMMR;
991425fe MB	67	u32 msize = 0;
	68
	69	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
	70	return -1;
	71
dc9e499c RJ	72	puts("Initializing\n");
dc9e499c RJ	73
991425fe MB	74	/* DDR SDRAM - Main SODIMM */
	75	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
	76	#if defined(CONFIG_SPD_EEPROM)
dc9e499c	77	msize = spd_sdram();
991425fe MB	78	#else
	79	msize = fixed_sdram();
	80	#endif
	81	/*
	82	* Initialize SDRAM if it is on local bus.
	83	*/
	84	sdram_init();
	85
	86	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	87	/*
	88	* Initialize and enable DDR ECC.
	89	*/
	90	ddr_enable_ecc(msize * 1024 * 1024);
	91	#endif
	92	puts(" DDR RAM: ");
	93	/* return total bus SDRAM size(bytes) -- DDR */
	94	return (msize * 1024 * 1024);
	95	}
	96
	97	#if !defined(CONFIG_SPD_EEPROM)
	98	/*************************************************************************
	99	* fixed sdram init -- doesn't use serial presence detect.
	100	************************************************************************/
	101	int fixed_sdram(void)
	102	{
d239d74b	103	volatile immap_t im = (immap_t )CFG_IMMR;
991425fe MB	104	u32 msize = 0;
	105	u32 ddr_size;
	106	u32 ddr_size_log2;
	107
	108	msize = CFG_DDR_SIZE;
	109	for (ddr_size = msize << 20, ddr_size_log2 = 0;
	110	(ddr_size > 1);
	111	ddr_size = ddr_size>>1, ddr_size_log2++) {
	112	if (ddr_size & 1) {
	113	return -1;
	114	}
	115	}
dc9e499c	116	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
991425fe	117	im->sysconf.ddrlaw[0].ar = LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
dc9e499c	118
991425fe MB	119	#if (CFG_DDR_SIZE != 256)
	120	#warning Currenly any ddr size other than 256 is not supported
	121	#endif
dc9e499c	122	im->ddr.csbnds[2].csbnds = 0x0000000f;
991425fe	123	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
dc9e499c	124
cf48eb9a	125	/* currently we use only one CS, so disable the other banks */
dc9e499c RJ	126	im->ddr.cs_config[0] = 0;
	127	im->ddr.cs_config[1] = 0;
	128	im->ddr.cs_config[3] = 0;
	129
	130	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
	131	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
cf48eb9a	132
991425fe MB	133	im->ddr.sdram_cfg =
	134	SDRAM_CFG_SREN
	135	#if defined(CONFIG_DDR_2T_TIMING)
	136	\| SDRAM_CFG_2T_EN
	137	#endif
	138	\| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
dc9e499c RJ	139	#if defined (CONFIG_DDR_32BIT)
	140	/* for 32-bit mode burst length is 8 */
	141	im->ddr.sdram_cfg \|= (SDRAM_CFG_32_BE \| SDRAM_CFG_8_BE);
	142	#endif
	143	im->ddr.sdram_mode = CFG_DDR_MODE;
991425fe	144
cf48eb9a	145	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
991425fe MB	146	udelay(200);
991425fe MB	147
dc9e499c	148	/* enable DDR controller */
991425fe	149	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
991425fe MB	150	return msize;
	151	}
	152	#endif/!CFG_SPD_EEPROM/
	153
	154
	155	int checkboard (void)
	156	{
	157	puts("Board: Freescale MPC8349EMDS\n");
	158	return 0;
	159	}
	160
991425fe MB	161	/*
	162	* if MPC8349EMDS is soldered with SDRAM
	163	*/
	164	#if defined(CFG_BR2_PRELIM) \
	165	&& defined(CFG_OR2_PRELIM) \
	166	&& defined(CFG_LBLAWBAR2_PRELIM) \
	167	&& defined(CFG_LBLAWAR2_PRELIM)
	168	/*
	169	* Initialize SDRAM memory on the Local Bus.
	170	*/
	171
	172	void sdram_init(void)
	173	{
d239d74b	174	volatile immap_t immap = (immap_t )CFG_IMMR;
f6eda7f8	175	volatile lbus83xx_t *lbc= &immap->lbus;
991425fe MB	176	uint sdram_addr = (uint )CFG_LBC_SDRAM_BASE;
	177
	178	puts("\n SDRAM on Local Bus: ");
	179	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
	180
	181	/*
	182	* Setup SDRAM Base and Option Registers, already done in cpu_init.c
	183	*/
	184
	185	/* setup mtrpt, lsrt and lbcr for LB bus */
	186	lbc->lbcr = CFG_LBC_LBCR;
	187	lbc->mrtpr = CFG_LBC_MRTPR;
	188	lbc->lsrt = CFG_LBC_LSRT;
	189	asm("sync");
	190
	191	/*
	192	* Configure the SDRAM controller Machine Mode Register.
	193	*/
	194	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
	195
	196	lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
	197	asm("sync");
	198	*sdram_addr = 0xff;
	199	udelay(100);
	200
	201	lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
	202	asm("sync");
	203	/1 times/
	204	*sdram_addr = 0xff;
	205	udelay(100);
	206	/2 times/
	207	*sdram_addr = 0xff;
	208	udelay(100);
	209	/3 times/
	210	*sdram_addr = 0xff;
	211	udelay(100);
	212	/4 times/
	213	*sdram_addr = 0xff;
	214	udelay(100);
	215	/5 times/
	216	*sdram_addr = 0xff;
	217	udelay(100);
	218	/6 times/
	219	*sdram_addr = 0xff;
	220	udelay(100);
	221	/7 times/
	222	*sdram_addr = 0xff;
	223	udelay(100);
	224	/8 times/
	225	*sdram_addr = 0xff;
	226	udelay(100);
	227
	228	/* 0x58636733; mode register write operation */
	229	lbc->lsdmr = CFG_LBC_LSDMR_4;
	230	asm("sync");
	231	*sdram_addr = 0xff;
	232	udelay(100);
	233
	234	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
	235	asm("sync");
	236	*sdram_addr = 0xff;
	237	udelay(100);
	238	}
	239	#else
240	void sdram_init(void)
241	{
242	put("SDRAM on Local Bus is NOT available!\n");
243	}
244	#endif
d326f4a2 MB	245
	246	#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
	247	/*
	248	* ECC user commands
	249	*/
	250	void ecc_print_status(void)
	251	{
d239d74b	252	volatile immap_t immap = (immap_t )CFG_IMMR;
f6eda7f8	253	volatile ddr83xx_t *ddr = &immap->ddr;
d326f4a2 MB	254
	255	printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
	256
	257	/* Interrupts */
	258	printf("Memory Error Interrupt Enable:\n");
	259	printf(" Multiple-Bit Error Interrupt Enable: %d\n",
	260	(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
	261	printf(" Single-Bit Error Interrupt Enable: %d\n",
	262	(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
	263	printf(" Memory Select Error Interrupt Enable: %d\n\n",
	264	(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
	265
	266	/* Error disable */
	267	printf("Memory Error Disable:\n");
	268	printf(" Multiple-Bit Error Disable: %d\n",
	269	(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
	270	printf(" Sinle-Bit Error Disable: %d\n",
	271	(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
	272	printf(" Memory Select Error Disable: %d\n\n",
	273	(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
	274
	275	/* Error injection */
	276	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
	277	ddr->data_err_inject_hi, ddr->data_err_inject_lo);
	278
	279	printf("Memory Data Path Error Injection Mask ECC:\n");
	280	printf(" ECC Mirror Byte: %d\n",
	281	(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
	282	printf(" ECC Injection Enable: %d\n",
	283	(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
	284	printf(" ECC Error Injection Mask: 0x%02x\n\n",
	285	ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
	286
	287	/* SBE counter/threshold */
	288	printf("Memory Single-Bit Error Management (0..255):\n");
	289	printf(" Single-Bit Error Threshold: %d\n",
	290	(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
	291	printf(" Single-Bit Error Counter: %d\n\n",
	292	(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
	293
	294	/* Error detect */
	295	printf("Memory Error Detect:\n");
	296	printf(" Multiple Memory Errors: %d\n",
	297	(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
	298	printf(" Multiple-Bit Error: %d\n",
	299	(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
	300	printf(" Single-Bit Error: %d\n",
	301	(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
	302	printf(" Memory Select Error: %d\n\n",
	303	(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
	304
	305	/* Capture data */
	306	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
	307	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
	308	ddr->capture_data_hi, ddr->capture_data_lo);
	309	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
	310	ddr->capture_ecc & CAPTURE_ECC_ECE);
	311
	312	printf("Memory Error Attributes Capture:\n");
	313	printf(" Data Beat Number: %d\n",
	314	(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
	315	printf(" Transaction Size: %d\n",
	316	(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
	317	printf(" Transaction Source: %d\n",
318	(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
319	printf(" Transaction Type: %d\n",
320	(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
321	printf(" Error Information Valid: %d\n\n",
322	ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
323	}
324
325	int do_ecc ( cmd_tbl_t cmdtp, int flag, int argc, char argv[])
326	{
d239d74b	327	volatile immap_t immap = (immap_t )CFG_IMMR;
f6eda7f8	328	volatile ddr83xx_t *ddr = &immap->ddr;
d326f4a2 MB	329	volatile u32 val;
	330	u64 *addr, count, val64;
	331	register u64 *i;
cf48eb9a	332
d326f4a2 MB	333	if (argc > 4) {
	334	printf ("Usage:\n%s\n", cmdtp->usage);
	335	return 1;
	336	}
cf48eb9a	337
d326f4a2 MB	338	if (argc == 2) {
	339	if (strcmp(argv[1], "status") == 0) {
	340	ecc_print_status();
	341	return 0;
	342	} else if (strcmp(argv[1], "captureclear") == 0) {
	343	ddr->capture_address = 0;
	344	ddr->capture_data_hi = 0;
	345	ddr->capture_data_lo = 0;
	346	ddr->capture_ecc = 0;
	347	ddr->capture_attributes = 0;
	348	return 0;
	349	}
cf48eb9a WD	350	}
cf48eb9a WD	351
d326f4a2 MB	352	if (argc == 3) {
	353	if (strcmp(argv[1], "sbecnt") == 0) {
	354	val = simple_strtoul(argv[2], NULL, 10);
	355	if (val > 255) {
	356	printf("Incorrect Counter value, should be 0..255\n");
	357	return 1;
	358	}
	359
	360	val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
	361	val \|= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
	362
	363	ddr->err_sbe = val;
	364	return 0;
	365	} else if (strcmp(argv[1], "sbethr") == 0) {
	366	val = simple_strtoul(argv[2], NULL, 10);
	367	if (val > 255) {
	368	printf("Incorrect Counter value, should be 0..255\n");
	369	return 1;
	370	}
	371
	372	val = (val << ECC_ERROR_MAN_SBET_SHIFT);
	373	val \|= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
	374
	375	ddr->err_sbe = val;
	376	return 0;
	377	} else if (strcmp(argv[1], "errdisable") == 0) {
	378	val = ddr->err_disable;
	379
	380	if (strcmp(argv[2], "+sbe") == 0) {
	381	val \|= ECC_ERROR_DISABLE_SBED;
	382	} else if (strcmp(argv[2], "+mbe") == 0) {
	383	val \|= ECC_ERROR_DISABLE_MBED;
	384	} else if (strcmp(argv[2], "+mse") == 0) {
	385	val \|= ECC_ERROR_DISABLE_MSED;
	386	} else if (strcmp(argv[2], "+all") == 0) {
cf48eb9a WD	387	val \|= (ECC_ERROR_DISABLE_SBED \|
cf48eb9a WD	388	ECC_ERROR_DISABLE_MBED \|
d326f4a2 MB	389	ECC_ERROR_DISABLE_MSED);
	390	} else if (strcmp(argv[2], "-sbe") == 0) {
	391	val &= ~ECC_ERROR_DISABLE_SBED;
	392	} else if (strcmp(argv[2], "-mbe") == 0) {
	393	val &= ~ECC_ERROR_DISABLE_MBED;
	394	} else if (strcmp(argv[2], "-mse") == 0) {
	395	val &= ~ECC_ERROR_DISABLE_MSED;
	396	} else if (strcmp(argv[2], "-all") == 0) {
cf48eb9a WD	397	val &= ~(ECC_ERROR_DISABLE_SBED \|
cf48eb9a WD	398	ECC_ERROR_DISABLE_MBED \|
d326f4a2 MB	399	ECC_ERROR_DISABLE_MSED);
	400	} else {
	401	printf("Incorrect err_disable field\n");
	402	return 1;
	403	}
	404
	405	ddr->err_disable = val;
	406	__asm__ __volatile__ ("sync");
	407	__asm__ __volatile__ ("isync");
	408	return 0;
	409	} else if (strcmp(argv[1], "errdetectclr") == 0) {
	410	val = ddr->err_detect;
	411
	412	if (strcmp(argv[2], "mme") == 0) {
	413	val \|= ECC_ERROR_DETECT_MME;
	414	} else if (strcmp(argv[2], "sbe") == 0) {
	415	val \|= ECC_ERROR_DETECT_SBE;
	416	} else if (strcmp(argv[2], "mbe") == 0) {
	417	val \|= ECC_ERROR_DETECT_MBE;
	418	} else if (strcmp(argv[2], "mse") == 0) {
	419	val \|= ECC_ERROR_DETECT_MSE;
	420	} else if (strcmp(argv[2], "all") == 0) {
	421	val \|= (ECC_ERROR_DETECT_MME \|
	422	ECC_ERROR_DETECT_MBE \|
	423	ECC_ERROR_DETECT_SBE \|
	424	ECC_ERROR_DETECT_MSE);
	425	} else {
	426	printf("Incorrect err_detect field\n");
	427	return 1;
	428	}
	429
	430	ddr->err_detect = val;
	431	return 0;
	432	} else if (strcmp(argv[1], "injectdatahi") == 0) {
	433	val = simple_strtoul(argv[2], NULL, 16);
	434
	435	ddr->data_err_inject_hi = val;
	436	return 0;
	437	} else if (strcmp(argv[1], "injectdatalo") == 0) {
	438	val = simple_strtoul(argv[2], NULL, 16);
	439
	440	ddr->data_err_inject_lo = val;
	441	return 0;
	442	} else if (strcmp(argv[1], "injectecc") == 0) {
	443	val = simple_strtoul(argv[2], NULL, 16);
	444	if (val > 0xff) {
	445	printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
	446	return 1;
	447	}
	448	val \|= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
	449
	450	ddr->ecc_err_inject = val;
	451	return 0;
	452	} else if (strcmp(argv[1], "inject") == 0) {
	453	val = ddr->ecc_err_inject;
	454
	455	if (strcmp(argv[2], "en") == 0)
	456	val \|= ECC_ERR_INJECT_EIEN;
	457	else if (strcmp(argv[2], "dis") == 0)
	458	val &= ~ECC_ERR_INJECT_EIEN;
	459	else
	460	printf("Incorrect command\n");
	461
	462	ddr->ecc_err_inject = val;
463	__asm__ __volatile__ ("sync");
464	__asm__ __volatile__ ("isync");
465	return 0;
466	} else if (strcmp(argv[1], "mirror") == 0) {
467	val = ddr->ecc_err_inject;
468
469	if (strcmp(argv[2], "en") == 0)
470	val \|= ECC_ERR_INJECT_EMB;
471	else if (strcmp(argv[2], "dis") == 0)
472	val &= ~ECC_ERR_INJECT_EMB;
473	else
474	printf("Incorrect command\n");
475
476	ddr->ecc_err_inject = val;
477	return 0;
478	}
479	}
480
481	if (argc == 4) {
482	if (strcmp(argv[1], "test") == 0) {
483	addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
484	count = simple_strtoul(argv[3], NULL, 16);
485
486	if ((u32)addr % 8) {
487	printf("Address not alligned on double word boundary\n");
488	return 1;
489	}
490
491	disable_interrupts();
492	icache_disable();
493
494	for (i = addr; i < addr + count; i++) {
495	/* enable injects */
496	ddr->ecc_err_inject \|= ECC_ERR_INJECT_EIEN;
497	__asm__ __volatile__ ("sync");
498	__asm__ __volatile__ ("isync");
499
500	/* write memory location injecting errors */
501	*i = 0x1122334455667788ULL;
502	__asm__ __volatile__ ("sync");
503
504	/* disable injects */
505	ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
506	__asm__ __volatile__ ("sync");
507	__asm__ __volatile__ ("isync");
508
509	/* read data, this generates ECC error */
510	val64 = *i;
511	__asm__ __volatile__ ("sync");
512
513	/* disable errors for ECC */
514	ddr->err_disable \|= ~ECC_ERROR_ENABLE;
515	__asm__ __volatile__ ("sync");
516	__asm__ __volatile__ ("isync");
517
518	/* re-initialize memory, write the location again
519	* NOT injecting errors this time */
520	*i = 0xcafecafecafecafeULL;
521	__asm__ __volatile__ ("sync");
522
523	/* enable errors for ECC */
524	ddr->err_disable &= ECC_ERROR_ENABLE;
525	__asm__ __volatile__ ("sync");
526	__asm__ __volatile__ ("isync");
527	}
528
529	icache_enable();
530	enable_interrupts();
531
532	return 0;
533	}
534	}
535
536	printf ("Usage:\n%s\n", cmdtp->usage);
537	return 1;
538	}
539
540	U_BOOT_CMD(
541	ecc, 4, 0, do_ecc,
542	"ecc - support for DDR ECC features\n",
543	"status - print out status info\n"
544	"ecc captureclear - clear capture regs data\n"
545	"ecc sbecnt <val> - set Single-Bit Error counter\n"
546	"ecc sbethr <val> - set Single-Bit Threshold\n"
547	"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
548	" [-\|+]sbe - Single-Bit Error\n"
549	" [-\|+]mbe - Multiple-Bit Error\n"
550	" [-\|+]mse - Memory Select Error\n"
551	" [-\|+]all - all errors\n"
552	"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
553	" mme - Multiple Memory Errors\n"
554	" sbe - Single-Bit Error\n"
555	" mbe - Multiple-Bit Error\n"
556	" mse - Memory Select Error\n"
557	" all - all errors\n"
558	"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
559	"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
560	"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
561	"ecc inject <en\|dis> - enable/disable error injection\n"
562	"ecc mirror <en\|dis> - enable/disable mirror byte\n"
563	"ecc test <addr> <cnt> - test mem region:\n"
564	" - enables injects\n"
565	" - writes pattern injecting errors\n"
566	" - disables injects\n"
567	" - reads pattern back, generates error\n"
568	" - re-inits memory"
569	);
570	#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
bf0b542d KP	571
	572	#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
	573	void
	574	ft_board_setup(void blob, bd_t bd)
	575	{
	576	u32 *p;
	577	int len;
	578
	579	#ifdef CONFIG_PCI
	580	ft_pci_setup(blob, bd);
	581	#endif
	582	ft_cpu_setup(blob, bd);
	583
	584	p = ft_get_prop(blob, "/memory/reg", &len);
	585	if (p != NULL) {
	586	*p++ = cpu_to_be32(bd->bi_memstart);
	587	*p = cpu_to_be32(bd->bi_memsize);
	588	}
	589	}
	590	#endif