[people/ms/u-boot.git] / board / mpc8540eval / mpc8540eval.c

/*
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>

long int fixed_sdram (void);

int board_pre_init (void)
{
#if defined(CONFIG_PCI)
	volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);

	pci->peer &= 0xffffffdf; /* disable master abort */
#endif
	return 0;
}

int checkboard (void)
{
	sys_info_t sysinfo;

	get_sys_info (&sysinfo);

	printf ("Board: Freescale MPC8540EVAL Board\n");
	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
		|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
		printf ("\tLBC: %lu MHz\n",
			sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
	} else {
		printf("\tLBC: unknown\n");
	}
	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
	return (0);
}

phys_size_t initdram (int board_type)
{
	long dram_size = 0;

#if !defined(CONFIG_RAM_AS_FLASH)
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	sys_info_t sysinfo;
	uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif

#if defined(CONFIG_DDR_DLL)
	uint temp_ddrdll = 0;

	/* Work around to stabilize DDR DLL */
	temp_ddrdll = gur->ddrdllcr;
	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
	asm("sync;isync;msync");
#endif

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;
#else
	dram_size = fixed_sdram ();
#endif

#if defined(CONFIG_SYS_RAMBOOT)
	return dram_size;
#endif

#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
	get_sys_info(&sysinfo);
	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
	if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
		lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
	} else {
		lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
		udelay(200);
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
		asm("sync;isync;msync");
	}
	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	* (ulong *)0 = 0x000000ff;
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
	asm("sync");
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("sync");
#endif

#if defined(CONFIG_DDR_ECC)
	{
		/* Initialize all of memory for ECC, then
		 * enable errors */
		uint *p = 0;
		uint i = 0;
		volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
		dma_init();
		for (*p = 0; p < (uint *)(8 * 1024); p++) {
			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
			*p = (unsigned int)0xdeadbeef;
			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
		}

		/* 8K */
		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
		/* 16K */
		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
		/* 32K */
		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
		/* 64K */
		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
		/* 128k */
		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
		/* 256k */
		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
		/* 512k */
		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
		/* 1M */
		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
		/* 2M */
		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
		/* 4M */
		dma_xfer((uint *)0x400000,0x400000,(uint *)0);

		for (i = 1; i < dram_size / 0x800000; i++) {
			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
		}

		/* Enable errors for ECC */
		ddr->err_disable = 0x00000000;
		asm("sync;isync;msync");
	}
#endif

	return dram_size;
}

#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test passed.\n");
	return 0;
}
#endif

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
#ifndef CONFIG_SYS_RAMBOOT
	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
#endif
	asm("sync;isync;msync");
	udelay(500);
#if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
#else
	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#endif
	asm("sync; isync; msync");
	udelay(500);
#endif
	return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */

int board_eth_init(bd_t *bis)
{
	/*
	 * This board either has PCI NICs or uses the CPU's TSECs
	 * pci_eth_init() will return 0 if no NICs found, so in that case
	 * returning -1 will force cpu_eth_init() to be called.
	 */
	int num = pci_eth_init(bis);
	return (num <= 0 ? -1 : num);
}
Commit	Line	Data
b0e32949 LW	1	/*
	2	* (C) Copyright 2002,2003, Motorola Inc.
	3	* Xianghua Xiao, (X.Xiao@motorola.com)
	4	*
	5	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
b0e32949	26	#include <common.h>
8ca0b3f9	27	#include <netdev.h>
b0e32949	28	#include <asm/processor.h>
9658bec2	29	#include <asm/mmu.h>
b0e32949	30	#include <asm/immap_85xx.h>
9658bec2	31	#include <asm/fsl_ddr_sdram.h>
a30a549a	32	#include <spd_sdram.h>
b0e32949 LW	33
	34	long int fixed_sdram (void);
	35
b0e32949 LW	36	int board_pre_init (void)
	37	{
	38	#if defined(CONFIG_PCI)
6d0f6bcf	39	volatile ccsr_pcix_t pci = (void )(CONFIG_SYS_MPC85xx_PCIX_ADDR);
b0e32949 LW	40
	41	pci->peer &= 0xffffffdf; /* disable master abort */
	42	#endif
	43	return 0;
	44	}
	45
	46	int checkboard (void)
	47	{
	48	sys_info_t sysinfo;
	49
	50	get_sys_info (&sysinfo);
	51
	52	printf ("Board: Freescale MPC8540EVAL Board\n");
	53	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
	54	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
	55	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
6d0f6bcf JCPV	56	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 \|\| (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
6d0f6bcf JCPV	57	\|\| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
de1d0a69	58	printf ("\tLBC: %lu MHz\n",
6d0f6bcf	59	sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
b0e32949 LW	60	} else {
	61	printf("\tLBC: unknown\n");
	62	}
	63	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
	64	return (0);
	65	}
	66
9973e3c6	67	phys_size_t initdram (int board_type)
b0e32949 LW	68	{
b0e32949 LW	69	long dram_size = 0;
a30a549a	70
b0e32949	71	#if !defined(CONFIG_RAM_AS_FLASH)
6d0f6bcf	72	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
b0e32949 LW	73	sys_info_t sysinfo;
	74	uint temp_lbcdll = 0;
	75	#endif
	76	#if !defined(CONFIG_RAM_AS_FLASH) \|\| defined(CONFIG_DDR_DLL)
6d0f6bcf	77	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
b0e32949 LW	78	#endif
	79
	80	#if defined(CONFIG_DDR_DLL)
	81	uint temp_ddrdll = 0;
	82
	83	/* Work around to stabilize DDR DLL */
	84	temp_ddrdll = gur->ddrdllcr;
	85	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) \| 0x80000000;
	86	asm("sync;isync;msync");
	87	#endif
	88
	89	#if defined(CONFIG_SPD_EEPROM)
9658bec2 KG	90	dram_size = fsl_ddr_sdram();
	91	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	92	dram_size *= 0x100000;
b0e32949 LW	93	#else
	94	dram_size = fixed_sdram ();
	95	#endif
	96
6d0f6bcf	97	#if defined(CONFIG_SYS_RAMBOOT)
b0e32949 LW	98	return dram_size;
	99	#endif
	100
	101	#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
	102	get_sys_info(&sysinfo);
	103	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
6d0f6bcf JCPV	104	if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
6d0f6bcf JCPV	105	lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)\| 0x80000000;
b0e32949	106	} else {
6d0f6bcf	107	lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
b0e32949 LW	108	udelay(200);
	109	temp_lbcdll = gur->lbcdllcr;
	110	gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) \| 0x80000000;
	111	asm("sync;isync;msync");
	112	}
6d0f6bcf JCPV	113	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
	114	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
	115	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	116	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
b0e32949 LW	117	asm("sync");
b0e32949 LW	118	* (ulong *)0 = 0x000000ff;
6d0f6bcf	119	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
b0e32949 LW	120	asm("sync");
b0e32949 LW	121	* (ulong *)0 = 0x000000ff;
6d0f6bcf	122	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
b0e32949 LW	123	asm("sync");
b0e32949 LW	124	* (ulong *)0 = 0x000000ff;
6d0f6bcf	125	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
b0e32949 LW	126	asm("sync");
b0e32949 LW	127	* (ulong *)0 = 0x000000ff;
6d0f6bcf	128	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
b0e32949	129	asm("sync");
6d0f6bcf	130	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
b0e32949	131	asm("sync");
6d0f6bcf	132	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
b0e32949 LW	133	asm("sync");
	134	#endif
	135
	136	#if defined(CONFIG_DDR_ECC)
	137	{
	138	/* Initialize all of memory for ECC, then
	139	* enable errors */
	140	uint *p = 0;
	141	uint i = 0;
6d0f6bcf	142	volatile ccsr_ddr_t ddr= (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
b0e32949 LW	143	dma_init();
	144	for (p = 0; p < (uint )(8 * 1024); p++) {
	145	if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
	146	*p = (unsigned int)0xdeadbeef;
	147	if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
	148	}
	149
	150	/* 8K */
	151	dma_xfer((uint )0x2000,0x2000,(uint )0);
	152	/* 16K */
	153	dma_xfer((uint )0x4000,0x4000,(uint )0);
	154	/* 32K */
	155	dma_xfer((uint )0x8000,0x8000,(uint )0);
	156	/* 64K */
	157	dma_xfer((uint )0x10000,0x10000,(uint )0);
	158	/* 128k */
	159	dma_xfer((uint )0x20000,0x20000,(uint )0);
	160	/* 256k */
	161	dma_xfer((uint )0x40000,0x40000,(uint )0);
	162	/* 512k */
	163	dma_xfer((uint )0x80000,0x80000,(uint )0);
	164	/* 1M */
	165	dma_xfer((uint )0x100000,0x100000,(uint )0);
	166	/* 2M */
	167	dma_xfer((uint )0x200000,0x200000,(uint )0);
	168	/* 4M */
	169	dma_xfer((uint )0x400000,0x400000,(uint )0);
	170
	171	for (i = 1; i < dram_size / 0x800000; i++) {
	172	dma_xfer((uint )(0x800000i),0x800000,(uint *)0);
	173	}
	174
	175	/* Enable errors for ECC */
	176	ddr->err_disable = 0x00000000;
	177	asm("sync;isync;msync");
	178	}
	179	#endif
	180
	181	return dram_size;
	182	}
	183
6d0f6bcf	184	#if defined(CONFIG_SYS_DRAM_TEST)
b0e32949 LW	185	int testdram (void)
b0e32949 LW	186	{
6d0f6bcf JCPV	187	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	188	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
b0e32949 LW	189	uint *p;
	190
	191	printf("SDRAM test phase 1:\n");
	192	for (p = pstart; p < pend; p++)
	193	*p = 0xaaaaaaaa;
	194
	195	for (p = pstart; p < pend; p++) {
	196	if (*p != 0xaaaaaaaa) {
	197	printf ("SDRAM test fails at: %08x\n", (uint) p);
	198	return 1;
	199	}
	200	}
	201
	202	printf("SDRAM test phase 2:\n");
	203	for (p = pstart; p < pend; p++)
	204	*p = 0x55555555;
	205
	206	for (p = pstart; p < pend; p++) {
	207	if (*p != 0x55555555) {
	208	printf ("SDRAM test fails at: %08x\n", (uint) p);
	209	return 1;
	210	}
	211	}
	212
	213	printf("SDRAM test passed.\n");
	214	return 0;
	215	}
	216	#endif
	217
b0e32949 LW	218	#if !defined(CONFIG_SPD_EEPROM)
	219	/*************************************************************************
	220	* fixed sdram init -- doesn't use serial presence detect.
	221	************************************************************************/
	222	long int fixed_sdram (void)
	223	{
6d0f6bcf JCPV	224	#ifndef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	225	volatile ccsr_ddr_t ddr= (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
b0e32949	226
6d0f6bcf JCPV	227	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	228	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	229	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	230	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	231	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	232	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
de1d0a69	233	#if defined (CONFIG_DDR_ECC)
b0e32949 LW	234	ddr->err_disable = 0x0000000D;
b0e32949 LW	235	ddr->err_sbe = 0x00ff0000;
de1d0a69	236	#endif
b0e32949 LW	237	asm("sync;isync;msync");
b0e32949 LW	238	udelay(500);
de1d0a69	239	#if defined (CONFIG_DDR_ECC)
b0e32949	240	/* Enable ECC checking */
6d0f6bcf	241	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL \| 0x20000000);
de1d0a69	242	#else
6d0f6bcf	243	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
de1d0a69	244	#endif
b0e32949 LW	245	asm("sync; isync; msync");
b0e32949 LW	246	udelay(500);
de1d0a69	247	#endif
6d0f6bcf	248	return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
b0e32949 LW	249	}
b0e32949 LW	250	#endif /* !defined(CONFIG_SPD_EEPROM) */
8ca0b3f9 BW	251
	252	int board_eth_init(bd_t *bis)
	253	{
	254	/*
	255	* This board either has PCI NICs or uses the CPU's TSECs
	256	* pci_eth_init() will return 0 if no NICs found, so in that case
	257	* returning -1 will force cpu_eth_init() to be called.
	258	*/
	259	int num = pci_eth_init(bis);
	260	return (num <= 0 ? -1 : num);
	261	}