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42d1f039 | 1 | /* |
97d80fc3 | 2 | * Copyright 2004 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2003,Motorola Inc. |
4 | * Xianghua Xiao, (X.Xiao@motorola.com) | |
5 | * | |
6 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | ||
28 | extern long int spd_sdram (void); | |
29 | ||
30 | #include <common.h> | |
31 | #include <asm/processor.h> | |
32 | #include <asm/immap_85xx.h> | |
33 | #include <ioports.h> | |
34 | #include <spd.h> | |
35 | #include <miiphy.h> | |
36 | ||
37 | long int fixed_sdram (void); | |
38 | ||
39 | /* | |
40 | * I/O Port configuration table | |
41 | * | |
42 | * if conf is 1, then that port pin will be configured at boot time | |
43 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
44 | */ | |
45 | ||
46 | const iop_conf_t iop_conf_tab[4][32] = { | |
47 | ||
48 | /* Port A configuration */ | |
49 | { /* conf ppar psor pdir podr pdat */ | |
50 | /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ | |
51 | /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ | |
52 | /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ | |
53 | /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ | |
54 | /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ | |
55 | /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ | |
56 | /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ | |
57 | /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ | |
58 | /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ | |
59 | /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ | |
60 | /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ | |
61 | /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ | |
62 | /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ | |
63 | /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ | |
64 | /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ | |
65 | /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ | |
66 | /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ | |
67 | /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ | |
68 | /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ | |
69 | /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ | |
70 | /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ | |
71 | /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ | |
72 | /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ | |
73 | /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ | |
74 | /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ | |
75 | /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ | |
76 | /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ | |
77 | /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ | |
78 | /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ | |
79 | /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ | |
80 | /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ | |
81 | /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ | |
82 | }, | |
83 | ||
84 | /* Port B configuration */ | |
85 | { /* conf ppar psor pdir podr pdat */ | |
86 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ | |
87 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ | |
88 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ | |
89 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ | |
90 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ | |
91 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ | |
92 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ | |
93 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ | |
94 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ | |
95 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ | |
96 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ | |
97 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ | |
98 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ | |
99 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ | |
100 | /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ | |
101 | /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ | |
102 | /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ | |
103 | /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ | |
104 | /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ | |
105 | /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ | |
106 | /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ | |
107 | /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ | |
108 | /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ | |
109 | /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ | |
110 | /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ | |
111 | /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ | |
112 | /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ | |
113 | /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ | |
114 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
115 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
116 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
117 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
118 | }, | |
119 | ||
120 | /* Port C */ | |
121 | { /* conf ppar psor pdir podr pdat */ | |
122 | /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ | |
123 | /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ | |
124 | /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ | |
125 | /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ | |
126 | /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ | |
127 | /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ | |
128 | /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ | |
129 | /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ | |
130 | /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ | |
131 | /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ | |
132 | /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ | |
133 | /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ | |
134 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ | |
135 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ | |
136 | /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ | |
137 | /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ | |
138 | /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ | |
139 | /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ | |
140 | /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ | |
141 | /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ | |
142 | /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ | |
143 | /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ | |
144 | /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ | |
145 | /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ | |
146 | /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ | |
147 | /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ | |
148 | /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ | |
149 | /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ | |
150 | /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ | |
151 | /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ | |
152 | /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ | |
153 | /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ | |
154 | }, | |
155 | ||
156 | /* Port D */ | |
157 | { /* conf ppar psor pdir podr pdat */ | |
158 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ | |
159 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ | |
160 | /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ | |
161 | /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ | |
162 | /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ | |
163 | /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ | |
164 | /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ | |
165 | /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ | |
166 | /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ | |
167 | /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ | |
168 | /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ | |
169 | /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ | |
170 | /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ | |
171 | /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ | |
172 | /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ | |
173 | /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ | |
174 | /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
175 | /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ | |
176 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ | |
177 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ | |
178 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ | |
179 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ | |
180 | /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ | |
181 | /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ | |
182 | /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ | |
183 | /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ | |
184 | /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ | |
185 | /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ | |
186 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
187 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
188 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
189 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
190 | } | |
191 | }; | |
192 | ||
193 | /* MPC8560ADS Board Status & Control Registers */ | |
194 | typedef struct bscr_ { | |
195 | volatile unsigned char bcsr0; | |
196 | volatile unsigned char bcsr1; | |
197 | volatile unsigned char bcsr2; | |
198 | volatile unsigned char bcsr3; | |
199 | volatile unsigned char bcsr4; | |
200 | volatile unsigned char bcsr5; | |
201 | } bcsr_t; | |
202 | ||
c837dcb1 | 203 | int board_early_init_f (void) |
42d1f039 WD |
204 | { |
205 | #if defined(CONFIG_PCI) | |
206 | volatile immap_t *immr = (immap_t *)CFG_IMMR; | |
207 | volatile ccsr_pcix_t *pci = &immr->im_pcix; | |
208 | ||
209 | pci->peer &= 0xfffffffdf; /* disable master abort */ | |
210 | #endif | |
211 | return 0; | |
212 | } | |
213 | ||
214 | void reset_phy (void) | |
215 | { | |
216 | #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ | |
217 | volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR; | |
218 | #endif | |
219 | /* reset Giga bit Ethernet port if needed here */ | |
220 | ||
221 | /* reset the CPM FEC port */ | |
222 | #if (CONFIG_ETHER_INDEX == 2) | |
223 | bcsr->bcsr2 &= ~FETH2_RST; | |
224 | udelay(2); | |
225 | bcsr->bcsr2 |= FETH2_RST; | |
226 | udelay(1000); | |
227 | #elif (CONFIG_ETHER_INDEX == 3) | |
228 | bcsr->bcsr3 &= ~FETH3_RST; | |
229 | udelay(2); | |
230 | bcsr->bcsr3 |= FETH3_RST; | |
231 | udelay(1000); | |
232 | #endif | |
233 | #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) | |
234 | miiphy_reset(0x0); /* reset PHY */ | |
235 | miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */ | |
236 | miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); | |
237 | #endif /* CONFIG_MII */ | |
238 | } | |
239 | ||
97d80fc3 | 240 | |
42d1f039 WD |
241 | int checkboard (void) |
242 | { | |
97d80fc3 WD |
243 | puts("Board: ADS\n"); |
244 | return 0; | |
42d1f039 WD |
245 | } |
246 | ||
247 | ||
248 | long int initdram (int board_type) | |
249 | { | |
250 | long dram_size = 0; | |
251 | extern long spd_sdram (void); | |
252 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
253 | #if !defined(CONFIG_RAM_AS_FLASH) | |
254 | volatile ccsr_lbc_t *lbc= &immap->im_lbc; | |
255 | sys_info_t sysinfo; | |
256 | uint temp_lbcdll = 0; | |
257 | #endif | |
258 | #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) | |
259 | volatile ccsr_gur_t *gur= &immap->im_gur; | |
260 | #endif | |
97d80fc3 | 261 | |
42d1f039 WD |
262 | #if defined(CONFIG_DDR_DLL) |
263 | uint temp_ddrdll = 0; | |
264 | ||
265 | /* Work around to stabilize DDR DLL */ | |
266 | temp_ddrdll = gur->ddrdllcr; | |
267 | gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; | |
268 | asm("sync;isync;msync"); | |
269 | #endif | |
270 | ||
271 | #if defined(CONFIG_SPD_EEPROM) | |
272 | dram_size = spd_sdram (); | |
273 | #else | |
274 | dram_size = fixed_sdram (); | |
275 | #endif | |
276 | ||
277 | #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ | |
278 | get_sys_info(&sysinfo); | |
279 | /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ | |
280 | if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { | |
281 | lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; | |
282 | } else { | |
97d80fc3 WD |
283 | uint pvr = get_pvr(); |
284 | ||
285 | if (pvr == PVR_85xx_REV1) { | |
286 | /* | |
287 | * Need change CLKDIV before enable DLL. | |
288 | * Default CLKDIV is 8, change it to 4 | |
289 | * temporarily. | |
290 | */ | |
291 | lbc->lcrr = 0x10000004; | |
292 | } | |
42d1f039 WD |
293 | lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; |
294 | udelay(200); | |
295 | temp_lbcdll = gur->lbcdllcr; | |
296 | gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; | |
297 | asm("sync;isync;msync"); | |
298 | } | |
299 | lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ | |
300 | lbc->br2 = CFG_BR2_PRELIM; | |
301 | lbc->lbcr = CFG_LBC_LBCR; | |
302 | lbc->lsdmr = CFG_LBC_LSDMR_1; | |
303 | asm("sync"); | |
304 | (unsigned int) * (ulong *)0 = 0x000000ff; | |
305 | lbc->lsdmr = CFG_LBC_LSDMR_2; | |
306 | asm("sync"); | |
307 | (unsigned int) * (ulong *)0 = 0x000000ff; | |
308 | lbc->lsdmr = CFG_LBC_LSDMR_3; | |
309 | asm("sync"); | |
310 | (unsigned int) * (ulong *)0 = 0x000000ff; | |
311 | lbc->lsdmr = CFG_LBC_LSDMR_4; | |
312 | asm("sync"); | |
313 | (unsigned int) * (ulong *)0 = 0x000000ff; | |
314 | lbc->lsdmr = CFG_LBC_LSDMR_5; | |
315 | asm("sync"); | |
316 | lbc->lsrt = CFG_LBC_LSRT; | |
317 | asm("sync"); | |
318 | lbc->mrtpr = CFG_LBC_MRTPR; | |
319 | asm("sync"); | |
320 | #endif | |
321 | ||
322 | #if defined(CONFIG_DDR_ECC) | |
323 | { | |
324 | /* Initialize all of memory for ECC, then | |
325 | * enable errors */ | |
326 | uint *p = 0; | |
327 | uint i = 0; | |
328 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
329 | volatile ccsr_ddr_t *ddr= &immap->im_ddr; | |
330 | dma_init(); | |
331 | for (*p = 0; p < (uint *)(8 * 1024); p++) { | |
332 | if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } | |
333 | *p = (unsigned int)0xdeadbeef; | |
334 | if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } | |
335 | } | |
336 | ||
337 | /* 8K */ | |
338 | dma_xfer((uint *)0x2000,0x2000,(uint *)0); | |
339 | /* 16K */ | |
340 | dma_xfer((uint *)0x4000,0x4000,(uint *)0); | |
341 | /* 32K */ | |
342 | dma_xfer((uint *)0x8000,0x8000,(uint *)0); | |
343 | /* 64K */ | |
344 | dma_xfer((uint *)0x10000,0x10000,(uint *)0); | |
345 | /* 128k */ | |
346 | dma_xfer((uint *)0x20000,0x20000,(uint *)0); | |
347 | /* 256k */ | |
348 | dma_xfer((uint *)0x40000,0x40000,(uint *)0); | |
349 | /* 512k */ | |
350 | dma_xfer((uint *)0x80000,0x80000,(uint *)0); | |
351 | /* 1M */ | |
352 | dma_xfer((uint *)0x100000,0x100000,(uint *)0); | |
353 | /* 2M */ | |
354 | dma_xfer((uint *)0x200000,0x200000,(uint *)0); | |
355 | /* 4M */ | |
356 | dma_xfer((uint *)0x400000,0x400000,(uint *)0); | |
357 | ||
358 | for (i = 1; i < dram_size / 0x800000; i++) { | |
359 | dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); | |
360 | } | |
361 | ||
362 | /* Enable errors for ECC */ | |
363 | ddr->err_disable = 0x00000000; | |
364 | asm("sync;isync;msync"); | |
365 | } | |
366 | #endif | |
367 | ||
368 | return dram_size; | |
369 | } | |
370 | ||
371 | ||
372 | #if defined(CFG_DRAM_TEST) | |
373 | int testdram (void) | |
374 | { | |
375 | uint *pstart = (uint *) CFG_MEMTEST_START; | |
376 | uint *pend = (uint *) CFG_MEMTEST_END; | |
377 | uint *p; | |
378 | ||
379 | printf("SDRAM test phase 1:\n"); | |
380 | for (p = pstart; p < pend; p++) | |
381 | *p = 0xaaaaaaaa; | |
382 | ||
383 | for (p = pstart; p < pend; p++) { | |
384 | if (*p != 0xaaaaaaaa) { | |
385 | printf ("SDRAM test fails at: %08x\n", (uint) p); | |
386 | return 1; | |
387 | } | |
388 | } | |
389 | ||
390 | printf("SDRAM test phase 2:\n"); | |
391 | for (p = pstart; p < pend; p++) | |
392 | *p = 0x55555555; | |
393 | ||
394 | for (p = pstart; p < pend; p++) { | |
395 | if (*p != 0x55555555) { | |
396 | printf ("SDRAM test fails at: %08x\n", (uint) p); | |
397 | return 1; | |
398 | } | |
399 | } | |
400 | ||
401 | printf("SDRAM test passed.\n"); | |
402 | return 0; | |
403 | } | |
404 | #endif | |
405 | ||
406 | #if !defined(CONFIG_SPD_EEPROM) | |
407 | /************************************************************************* | |
408 | * fixed sdram init -- doesn't use serial presence detect. | |
409 | ************************************************************************/ | |
410 | long int fixed_sdram (void) | |
411 | { | |
412 | #ifndef CFG_RAMBOOT | |
413 | volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
414 | volatile ccsr_ddr_t *ddr= &immap->im_ddr; | |
415 | ||
416 | ddr->cs0_bnds = CFG_DDR_CS0_BNDS; | |
417 | ddr->cs0_config = CFG_DDR_CS0_CONFIG; | |
418 | ddr->timing_cfg_1 = CFG_DDR_TIMING_1; | |
419 | ddr->timing_cfg_2 = CFG_DDR_TIMING_2; | |
420 | ddr->sdram_mode = CFG_DDR_MODE; | |
421 | ddr->sdram_interval = CFG_DDR_INTERVAL; | |
422 | #if defined (CONFIG_DDR_ECC) | |
423 | ddr->err_disable = 0x0000000D; | |
424 | ddr->err_sbe = 0x00ff0000; | |
425 | #endif | |
426 | asm("sync;isync;msync"); | |
427 | udelay(500); | |
428 | #if defined (CONFIG_DDR_ECC) | |
429 | /* Enable ECC checking */ | |
430 | ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); | |
431 | #else | |
432 | ddr->sdram_cfg = CFG_DDR_CONTROL; | |
433 | #endif | |
434 | asm("sync; isync; msync"); | |
435 | udelay(500); | |
436 | #endif | |
437 | return ( CFG_SDRAM_SIZE * 1024 * 1024); | |
438 | } | |
439 | #endif /* !defined(CONFIG_SPD_EEPROM) */ |