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* Patches by Xianghua Xiao, 15 Oct 2003:
[people/ms/u-boot.git] / board / mpc8560ads / mpc8560ads.c
CommitLineData
42d1f039
WD		 1/*
2 * (C) Copyright 2003,Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27extern long int spd_sdram (void);
28
29#include <common.h>
30#include <asm/processor.h>
31#include <asm/immap_85xx.h>
32#include <ioports.h>
33#include <spd.h>
34#include <miiphy.h>
35
36long int fixed_sdram (void);
37
38/*
39 * I/O Port configuration table
40 *
41 * if conf is 1, then that port pin will be configured at boot time
42 * according to the five values podr/pdir/ppar/psor/pdat for that entry
43 */
44
45const iop_conf_t iop_conf_tab[4][32] = {
46
47 /* Port A configuration */
48 { /* conf ppar psor pdir podr pdat */
49 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
50 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
51 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
52 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
53 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
54 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
55 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
56 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
57 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
58 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
59 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
60 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
61 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
62 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
63 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
64 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
65 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
66 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
67 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
68 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
69 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
70 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
71 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
72 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
73 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
74 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
75 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
76 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
77 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
78 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
79 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
80 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
81 },
82
83 /* Port B configuration */
84 { /* conf ppar psor pdir podr pdat */
85 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
86 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
87 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
88 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
89 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
90 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
91 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
92 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
93 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
94 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
95 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
96 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
97 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
98 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
99 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
100 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
101 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
102 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
103 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
104 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
105 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
106 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
107 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
108 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
109 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
110 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
111 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
112 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
113 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
114 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
115 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
116 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
117 },
118
119 /* Port C */
120 { /* conf ppar psor pdir podr pdat */
121 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
122 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
123 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
124 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
125 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
126 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
127 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
128 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
129 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
130 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
131 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
132 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
133 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
134 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
135 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
136 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
137 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
138 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
139 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
140 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
141 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
142 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
143 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
144 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
145 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
146 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
147 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
148 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
149 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
150 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
151 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
152 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
153 },
154
155 /* Port D */
156 { /* conf ppar psor pdir podr pdat */
157 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
158 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
159 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
160 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
161 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
162 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
163 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
164 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
165 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
166 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
167 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
168 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
169 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
170 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
171 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
172 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
173 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
174 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
175 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
176 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
177 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
178 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
179 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
180 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
181 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
182 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
183 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
184 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
185 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
186 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
187 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
188 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
189 }
190};
191
192/* MPC8560ADS Board Status & Control Registers */
193typedef struct bscr_ {
194 volatile unsigned char bcsr0;
195 volatile unsigned char bcsr1;
196 volatile unsigned char bcsr2;
197 volatile unsigned char bcsr3;
198 volatile unsigned char bcsr4;
199 volatile unsigned char bcsr5;
200} bcsr_t;
201
202int board_pre_init (void)
203{
204#if defined(CONFIG_PCI)
205 volatile immap_t *immr = (immap_t *)CFG_IMMR;
206 volatile ccsr_pcix_t *pci = &immr->im_pcix;
207
208 pci->peer &= 0xfffffffdf; /* disable master abort */
209#endif
210 return 0;
211}
212
213void reset_phy (void)
214{
215#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
216 volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
217#endif
218 /* reset Giga bit Ethernet port if needed here */
219
220 /* reset the CPM FEC port */
221#if (CONFIG_ETHER_INDEX == 2)
222 bcsr->bcsr2 &= ~FETH2_RST;
223 udelay(2);
224 bcsr->bcsr2 |= FETH2_RST;
225 udelay(1000);
226#elif (CONFIG_ETHER_INDEX == 3)
227 bcsr->bcsr3 &= ~FETH3_RST;
228 udelay(2);
229 bcsr->bcsr3 |= FETH3_RST;
230 udelay(1000);
231#endif
232#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
233 miiphy_reset(0x0); /* reset PHY */
234 miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
235 miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
236#endif /* CONFIG_MII */
237}
238
239int checkboard (void)
240{
241 sys_info_t sysinfo;
242
243 get_sys_info (&sysinfo);
244
245 printf ("Board: Motorola MPC8560ADS Board\n");
246 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
247 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
248 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
249 if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
250 || (CFG_LBC_LCRR & 0x0f) == 8) {
251 printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
252 } else {
253 printf("\tLBC: unknown\n");
254 }
255 printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
256 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
257
258 return (0);
259}
260
261
262long int initdram (int board_type)
263{
264 long dram_size = 0;
265 extern long spd_sdram (void);
266 volatile immap_t *immap = (immap_t *)CFG_IMMR;
267#if !defined(CONFIG_RAM_AS_FLASH)
268 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
269 sys_info_t sysinfo;
270 uint temp_lbcdll = 0;
271#endif
272#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
273 volatile ccsr_gur_t *gur= &immap->im_gur;
274#endif
275#if defined(CONFIG_DDR_DLL)
276 uint temp_ddrdll = 0;
277
278 /* Work around to stabilize DDR DLL */
279 temp_ddrdll = gur->ddrdllcr;
280 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
281 asm("sync;isync;msync");
282#endif
283
284#if defined(CONFIG_SPD_EEPROM)
285 dram_size = spd_sdram ();
286#else
287 dram_size = fixed_sdram ();
288#endif
289
290#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
291 get_sys_info(&sysinfo);
292 /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
293 if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
294 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
295 } else {
296#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
297 lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
298#endif
299 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
300 udelay(200);
301 temp_lbcdll = gur->lbcdllcr;
302 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
303 asm("sync;isync;msync");
304 }
305 lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
306 lbc->br2 = CFG_BR2_PRELIM;
307 lbc->lbcr = CFG_LBC_LBCR;
308 lbc->lsdmr = CFG_LBC_LSDMR_1;
309 asm("sync");
310 (unsigned int) * (ulong *)0 = 0x000000ff;
311 lbc->lsdmr = CFG_LBC_LSDMR_2;
312 asm("sync");
313 (unsigned int) * (ulong *)0 = 0x000000ff;
314 lbc->lsdmr = CFG_LBC_LSDMR_3;
315 asm("sync");
316 (unsigned int) * (ulong *)0 = 0x000000ff;
317 lbc->lsdmr = CFG_LBC_LSDMR_4;
318 asm("sync");
319 (unsigned int) * (ulong *)0 = 0x000000ff;
320 lbc->lsdmr = CFG_LBC_LSDMR_5;
321 asm("sync");
322 lbc->lsrt = CFG_LBC_LSRT;
323 asm("sync");
324 lbc->mrtpr = CFG_LBC_MRTPR;
325 asm("sync");
326#endif
327
328#if defined(CONFIG_DDR_ECC)
329 {
330 /* Initialize all of memory for ECC, then
331 * enable errors */
332 uint *p = 0;
333 uint i = 0;
334 volatile immap_t *immap = (immap_t *)CFG_IMMR;
335 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
336 dma_init();
337 for (*p = 0; p < (uint *)(8 * 1024); p++) {
338 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
339 *p = (unsigned int)0xdeadbeef;
340 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
341 }
342
343 /* 8K */
344 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
345 /* 16K */
346 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
347 /* 32K */
348 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
349 /* 64K */
350 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
351 /* 128k */
352 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
353 /* 256k */
354 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
355 /* 512k */
356 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
357 /* 1M */
358 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
359 /* 2M */
360 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
361 /* 4M */
362 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
363
364 for (i = 1; i < dram_size / 0x800000; i++) {
365 dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
366 }
367
368 /* Enable errors for ECC */
369 ddr->err_disable = 0x00000000;
370 asm("sync;isync;msync");
371 }
372#endif
373
374 return dram_size;
375}
376
377
378#if defined(CFG_DRAM_TEST)
379int testdram (void)
380{
381 uint *pstart = (uint *) CFG_MEMTEST_START;
382 uint *pend = (uint *) CFG_MEMTEST_END;
383 uint *p;
384
385 printf("SDRAM test phase 1:\n");
386 for (p = pstart; p < pend; p++)
387 *p = 0xaaaaaaaa;
388
389 for (p = pstart; p < pend; p++) {
390 if (*p != 0xaaaaaaaa) {
391 printf ("SDRAM test fails at: %08x\n", (uint) p);
392 return 1;
393 }
394 }
395
396 printf("SDRAM test phase 2:\n");
397 for (p = pstart; p < pend; p++)
398 *p = 0x55555555;
399
400 for (p = pstart; p < pend; p++) {
401 if (*p != 0x55555555) {
402 printf ("SDRAM test fails at: %08x\n", (uint) p);
403 return 1;
404 }
405 }
406
407 printf("SDRAM test passed.\n");
408 return 0;
409}
410#endif
411
412#if !defined(CONFIG_SPD_EEPROM)
413/*************************************************************************
414 * fixed sdram init -- doesn't use serial presence detect.
415 ************************************************************************/
416long int fixed_sdram (void)
417{
418 #ifndef CFG_RAMBOOT
419 volatile immap_t *immap = (immap_t *)CFG_IMMR;
420 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
421
422 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
423 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
424 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
425 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
426 ddr->sdram_mode = CFG_DDR_MODE;
427 ddr->sdram_interval = CFG_DDR_INTERVAL;
428 #if defined (CONFIG_DDR_ECC)
429 ddr->err_disable = 0x0000000D;
430 ddr->err_sbe = 0x00ff0000;
431 #endif
432 asm("sync;isync;msync");
433 udelay(500);
434 #if defined (CONFIG_DDR_ECC)
435 /* Enable ECC checking */
436 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
437 #else
438 ddr->sdram_cfg = CFG_DDR_CONTROL;
439 #endif
440 asm("sync; isync; msync");
441 udelay(500);
442 #endif
443 return ( CFG_SDRAM_SIZE * 1024 * 1024);
444}
445#endif /* !defined(CONFIG_SPD_EEPROM) */
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