]>
Commit | Line | Data |
---|---|---|
858b1a64 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * | |
24 | * TODO: clean-up | |
25 | */ | |
26 | ||
27 | /* | |
28 | * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? | |
29 | * | |
30 | * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being | |
31 | * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum | |
32 | * parameters from the datasheet are: | |
33 | * Tclk = 7.5ns (CL = 2) | |
34 | * Trp = 15ns | |
35 | * Trc = 60ns | |
36 | * Trcd = 15ns | |
37 | * Trfc = 66ns | |
38 | * | |
39 | * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock | |
40 | * period is 10ns and the parameters needed for the Timing Register are: | |
41 | * CASL = CL = 2 clock cycles | |
42 | * PTA = Trp = 15ns / 10ns = 2 clock cycles | |
43 | * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles | |
44 | * LDF = 2 clock cycles (but can be extended to meet board-level timing) | |
45 | * RFTA = Trfc = 66ns / 10ns= 7 clock cycles | |
46 | * RCD = Trcd = 15ns / 10ns= 2 clock cycles | |
47 | * | |
48 | * The actual bit settings in the register would be: | |
49 | * | |
50 | * CASL = 0b01 | |
51 | * PTA = 0b01 | |
52 | * CTP = 0b10 | |
53 | * LDF = 0b01 | |
54 | * RFTA = 0b011 | |
55 | * RCD = 0b01 | |
56 | * | |
57 | * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc | |
58 | * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay | |
59 | * defined as Trc rather than Trfc. | |
60 | * When using DIMM modules, most but not all of the required timing parameters can be read | |
61 | * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc | |
62 | * are not available from the EEPROM | |
63 | */ | |
64 | ||
65 | #include <common.h> | |
66 | #include "mip405.h" | |
67 | #include <asm/processor.h> | |
68 | #include <405gp_i2c.h> | |
69 | #include <miiphy.h> | |
70 | #include "../common/common_util.h" | |
71 | #include <i2c.h> | |
72 | extern block_dev_desc_t * scsi_get_dev(int dev); | |
73 | extern block_dev_desc_t * ide_get_dev(int dev); | |
74 | ||
75 | #undef SDRAM_DEBUG | |
f3e0de60 | 76 | #define ENABLE_ECC /* for ecc boards */ |
858b1a64 WD |
77 | #define FALSE 0 |
78 | #define TRUE 1 | |
79 | ||
80 | /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ | |
81 | #ifndef __ldiv_t_defined | |
82 | typedef struct { | |
83 | long int quot; /* Quotient */ | |
84 | long int rem; /* Remainder */ | |
85 | } ldiv_t; | |
86 | extern ldiv_t ldiv (long int __numer, long int __denom); | |
87 | # define __ldiv_t_defined 1 | |
88 | #endif | |
89 | ||
90 | ||
91 | #define PLD_PART_REG PER_PLD_ADDR + 0 | |
92 | #define PLD_VERS_REG PER_PLD_ADDR + 1 | |
93 | #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 | |
94 | #define PLD_IRQ_REG PER_PLD_ADDR + 3 | |
95 | #define PLD_COM_MODE_REG PER_PLD_ADDR + 4 | |
96 | #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 | |
97 | ||
98 | #define MEGA_BYTE (1024*1024) | |
99 | ||
100 | typedef struct { | |
101 | unsigned char boardtype; /* Board revision and Population Options */ | |
102 | unsigned char cal; /* cas Latency (will be programmend as cal-1) */ | |
103 | unsigned char trp; /* datain27 in clocks */ | |
104 | unsigned char trcd; /* datain29 in clocks */ | |
105 | unsigned char tras; /* datain30 in clocks */ | |
106 | unsigned char tctp; /* tras - trcd in clocks */ | |
107 | unsigned char am; /* Address Mod (will be programmed as am-1) */ | |
108 | unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */ | |
109 | unsigned char ecc; /* if true, ecc is enabled */ | |
110 | } sdram_t; | |
f3e0de60 WD |
111 | #if defined(CONFIG_MIP405T) |
112 | const sdram_t sdram_table[] = { | |
113 | { 0x01, /* MIP405T Rev A, 64MByte -1 Board */ | |
114 | 3, /* Case Latenty = 3 */ | |
115 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
116 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
117 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
118 | 4, /* tcpt 44 - 20ns = 24ns */ | |
119 | 3, /* Address Mode = 3 (13x9x4) */ | |
120 | 4, /* size value (64MByte) */ | |
121 | 0}, /* ECC disabled */ | |
122 | { 0xff, /* terminator */ | |
123 | 0xff, | |
124 | 0xff, | |
125 | 0xff, | |
126 | 0xff, | |
127 | 0xff, | |
128 | 0xff, | |
129 | 0xff } | |
130 | }; | |
131 | #else | |
858b1a64 WD |
132 | const sdram_t sdram_table[] = { |
133 | { 0x0f, /* Rev A, 128MByte -1 Board */ | |
134 | 3, /* Case Latenty = 3 */ | |
135 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
136 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
137 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
858b1a64 | 138 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 | 139 | 3, /* Address Mode = 3 */ |
858b1a64 WD |
140 | 5, /* size value */ |
141 | 1}, /* ECC enabled */ | |
142 | { 0x07, /* Rev A, 64MByte -2 Board */ | |
143 | 3, /* Case Latenty = 3 */ | |
144 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
145 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
146 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
858b1a64 | 147 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 | 148 | 2, /* Address Mode = 2 */ |
858b1a64 WD |
149 | 4, /* size value */ |
150 | 1}, /* ECC enabled */ | |
3e38691e WD |
151 | { 0x03, /* Rev A, 128MByte -4 Board */ |
152 | 3, /* Case Latenty = 3 */ | |
153 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
154 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
155 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
3e38691e | 156 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 WD |
157 | 3, /* Address Mode = 3 */ |
158 | 5, /* size value */ | |
159 | 1}, /* ECC enabled */ | |
160 | { 0x1f, /* Rev B, 128MByte -3 Board */ | |
161 | 3, /* Case Latenty = 3 */ | |
162 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
163 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
164 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
165 | 4, /* tcpt 44 - 20ns = 24ns */ | |
166 | 3, /* Address Mode = 3 */ | |
3e38691e WD |
167 | 5, /* size value */ |
168 | 1}, /* ECC enabled */ | |
858b1a64 WD |
169 | { 0xff, /* terminator */ |
170 | 0xff, | |
171 | 0xff, | |
172 | 0xff, | |
173 | 0xff, | |
174 | 0xff, | |
175 | 0xff, | |
176 | 0xff } | |
177 | }; | |
f3e0de60 | 178 | #endif /*CONFIG_MIP405T */ |
858b1a64 WD |
179 | void SDRAM_err (const char *s) |
180 | { | |
181 | #ifndef SDRAM_DEBUG | |
182 | DECLARE_GLOBAL_DATA_PTR; | |
183 | ||
184 | (void) get_clocks (); | |
185 | gd->baudrate = 9600; | |
186 | serial_init (); | |
187 | #endif | |
188 | serial_puts ("\n"); | |
189 | serial_puts (s); | |
190 | serial_puts ("\n enable SDRAM_DEBUG for more info\n"); | |
191 | for (;;); | |
192 | } | |
193 | ||
194 | ||
195 | unsigned char get_board_revcfg (void) | |
196 | { | |
197 | out8 (PER_BOARD_ADDR, 0); | |
198 | return (in8 (PER_BOARD_ADDR)); | |
199 | } | |
200 | ||
201 | ||
202 | #ifdef SDRAM_DEBUG | |
203 | ||
204 | void write_hex (unsigned char i) | |
205 | { | |
206 | char cc; | |
207 | ||
208 | cc = i >> 4; | |
209 | cc &= 0xf; | |
210 | if (cc > 9) | |
211 | serial_putc (cc + 55); | |
212 | else | |
213 | serial_putc (cc + 48); | |
214 | cc = i & 0xf; | |
215 | if (cc > 9) | |
216 | serial_putc (cc + 55); | |
217 | else | |
218 | serial_putc (cc + 48); | |
219 | } | |
220 | ||
221 | void write_4hex (unsigned long val) | |
222 | { | |
223 | write_hex ((unsigned char) (val >> 24)); | |
224 | write_hex ((unsigned char) (val >> 16)); | |
225 | write_hex ((unsigned char) (val >> 8)); | |
226 | write_hex ((unsigned char) val); | |
227 | } | |
228 | ||
229 | #endif | |
230 | ||
231 | ||
232 | int init_sdram (void) | |
233 | { | |
234 | DECLARE_GLOBAL_DATA_PTR; | |
235 | ||
236 | unsigned long tmp, baseaddr; | |
237 | unsigned short i; | |
238 | unsigned char trp_clocks, | |
239 | trcd_clocks, | |
240 | tras_clocks, | |
241 | trc_clocks, | |
242 | tctp_clocks; | |
243 | unsigned char cal_val; | |
244 | unsigned char bc; | |
f3e0de60 | 245 | unsigned long sdram_tim, sdram_bank; |
858b1a64 | 246 | |
f3e0de60 | 247 | /*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/ |
858b1a64 WD |
248 | (void) get_clocks (); |
249 | gd->baudrate = 9600; | |
250 | serial_init (); | |
f3e0de60 WD |
251 | /* set up the pld */ |
252 | mtdcr (ebccfga, pb7ap); | |
253 | mtdcr (ebccfgd, PLD_AP); | |
254 | mtdcr (ebccfga, pb7cr); | |
255 | mtdcr (ebccfgd, PLD_CR); | |
256 | /* THIS IS OBSOLETE */ | |
257 | /* set up the board rev reg*/ | |
258 | mtdcr (ebccfga, pb5ap); | |
259 | mtdcr (ebccfgd, BOARD_AP); | |
260 | mtdcr (ebccfga, pb5cr); | |
261 | mtdcr (ebccfgd, BOARD_CR); | |
262 | #ifdef SDRAM_DEBUG | |
263 | /* get all informations from PLD */ | |
264 | serial_puts ("\nPLD Part 0x"); | |
265 | bc = in8 (PLD_PART_REG); | |
266 | write_hex (bc); | |
267 | serial_puts ("\nPLD Vers 0x"); | |
268 | bc = in8 (PLD_VERS_REG); | |
269 | write_hex (bc); | |
270 | serial_puts ("\nBoard Rev 0x"); | |
271 | bc = in8 (PLD_BOARD_CFG_REG); | |
272 | write_hex (bc); | |
273 | serial_puts ("\n"); | |
274 | #endif | |
275 | /* check board */ | |
276 | bc = in8 (PLD_PART_REG); | |
277 | #if defined(CONFIG_MIP405T) | |
278 | if((bc & 0x80)==0) | |
279 | SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n"); | |
280 | #else | |
281 | if((bc & 0x80)==0x80) | |
282 | SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); | |
283 | #endif | |
284 | #if !defined(CONFIG_MIP405T) | |
285 | /* since the ECC initialisation needs some time, | |
286 | * we show that we're alive | |
287 | */ | |
858b1a64 | 288 | serial_puts ("\nInitializing SDRAM, Please stand by"); |
f3e0de60 | 289 | /* set-up the chipselect machine */ |
858b1a64 | 290 | mtdcr (ebccfga, pb0cr); /* get cs0 config reg */ |
f3e0de60 WD |
291 | tmp = mfdcr (ebccfgd); |
292 | if ((tmp & 0x00002000) == 0) { | |
858b1a64 WD |
293 | /* MPS Boot, set up the flash */ |
294 | mtdcr (ebccfga, pb1ap); | |
295 | mtdcr (ebccfgd, FLASH_AP); | |
296 | mtdcr (ebccfga, pb1cr); | |
297 | mtdcr (ebccfgd, FLASH_CR); | |
298 | } else { | |
299 | /* Flash boot, set up the MPS */ | |
300 | mtdcr (ebccfga, pb1ap); | |
301 | mtdcr (ebccfgd, MPS_AP); | |
302 | mtdcr (ebccfga, pb1cr); | |
303 | mtdcr (ebccfgd, MPS_CR); | |
304 | } | |
305 | /* set up UART0 (CS2) and UART1 (CS3) */ | |
306 | mtdcr (ebccfga, pb2ap); | |
307 | mtdcr (ebccfgd, UART0_AP); | |
308 | mtdcr (ebccfga, pb2cr); | |
309 | mtdcr (ebccfgd, UART0_CR); | |
310 | mtdcr (ebccfga, pb3ap); | |
311 | mtdcr (ebccfgd, UART1_AP); | |
312 | mtdcr (ebccfga, pb3cr); | |
313 | mtdcr (ebccfgd, UART1_CR); | |
858b1a64 | 314 | #endif |
f3e0de60 | 315 | bc = in8 (PLD_BOARD_CFG_REG); |
858b1a64 WD |
316 | #ifdef SDRAM_DEBUG |
317 | serial_puts ("\nstart SDRAM Setup\n"); | |
318 | serial_puts ("\nBoard Rev: "); | |
319 | write_hex (bc); | |
320 | serial_puts ("\n"); | |
321 | #endif | |
322 | i = 0; | |
323 | baseaddr = CFG_SDRAM_BASE; | |
324 | while (sdram_table[i].sz != 0xff) { | |
325 | if (sdram_table[i].boardtype == bc) | |
326 | break; | |
327 | i++; | |
328 | } | |
329 | if (sdram_table[i].boardtype != bc) | |
330 | SDRAM_err ("No SDRAM table found for this board!!!\n"); | |
331 | #ifdef SDRAM_DEBUG | |
332 | serial_puts (" found table "); | |
333 | write_hex (i); | |
334 | serial_puts (" \n"); | |
335 | #endif | |
336 | cal_val = sdram_table[i].cal - 1; /* Cas Latency */ | |
337 | trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */ | |
338 | trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ | |
339 | tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ | |
340 | /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ | |
341 | tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */ | |
342 | /* trc_clocks is sum of trp_clocks + tras_clocks */ | |
343 | trc_clocks = trp_clocks + tras_clocks; | |
344 | /* get SDRAM timing register */ | |
345 | mtdcr (memcfga, mem_sdtr1); | |
346 | sdram_tim = mfdcr (memcfgd) & ~0x018FC01F; | |
347 | /* insert CASL value */ | |
348 | sdram_tim |= ((unsigned long) (cal_val)) << 23; | |
349 | /* insert PTA value */ | |
350 | sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18; | |
351 | /* insert CTP value */ | |
352 | sdram_tim |= | |
353 | ((unsigned long) (trc_clocks - trp_clocks - | |
354 | trcd_clocks)) << 16; | |
355 | /* insert LDF (always 01) */ | |
356 | sdram_tim |= ((unsigned long) 0x01) << 14; | |
357 | /* insert RFTA value */ | |
358 | sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2; | |
359 | /* insert RCD value */ | |
360 | sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0; | |
361 | ||
362 | tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */ | |
363 | /* insert SZ value; */ | |
364 | tmp |= ((unsigned long) sdram_table[i].sz << 17); | |
365 | /* get SDRAM bank 0 register */ | |
366 | mtdcr (memcfga, mem_mb0cf); | |
367 | sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001; | |
368 | sdram_bank |= (baseaddr | tmp | 0x01); | |
369 | ||
370 | #ifdef SDRAM_DEBUG | |
371 | serial_puts ("sdtr: "); | |
372 | write_4hex (sdram_tim); | |
373 | serial_puts ("\n"); | |
374 | #endif | |
375 | ||
376 | /* write SDRAM timing register */ | |
377 | mtdcr (memcfga, mem_sdtr1); | |
378 | mtdcr (memcfgd, sdram_tim); | |
379 | ||
380 | #ifdef SDRAM_DEBUG | |
381 | serial_puts ("mb0cf: "); | |
382 | write_4hex (sdram_bank); | |
383 | serial_puts ("\n"); | |
384 | #endif | |
385 | ||
386 | /* write SDRAM bank 0 register */ | |
387 | mtdcr (memcfga, mem_mb0cf); | |
388 | mtdcr (memcfgd, sdram_bank); | |
389 | ||
390 | if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ | |
391 | /* get SDRAM refresh interval register */ | |
392 | mtdcr (memcfga, mem_rtr); | |
393 | tmp = mfdcr (memcfgd) & ~0x3FF80000; | |
394 | tmp |= 0x07F00000; | |
395 | } else { | |
396 | /* get SDRAM refresh interval register */ | |
397 | mtdcr (memcfga, mem_rtr); | |
398 | tmp = mfdcr (memcfgd) & ~0x3FF80000; | |
399 | tmp |= 0x05F00000; | |
400 | } | |
401 | /* write SDRAM refresh interval register */ | |
402 | mtdcr (memcfga, mem_rtr); | |
403 | mtdcr (memcfgd, tmp); | |
404 | /* enable ECC if used */ | |
f3e0de60 | 405 | #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) |
858b1a64 WD |
406 | if (sdram_table[i].ecc) { |
407 | /* disable checking for all banks */ | |
f3e0de60 | 408 | unsigned long *p; |
858b1a64 WD |
409 | #ifdef SDRAM_DEBUG |
410 | serial_puts ("disable ECC.. "); | |
411 | #endif | |
412 | mtdcr (memcfga, mem_ecccf); | |
413 | tmp = mfdcr (memcfgd); | |
414 | tmp &= 0xff0fffff; /* disable all banks */ | |
415 | mtdcr (memcfga, mem_ecccf); | |
416 | /* set up SDRAM Controller with ECC enabled */ | |
417 | #ifdef SDRAM_DEBUG | |
418 | serial_puts ("setup SDRAM Controller.. "); | |
419 | #endif | |
420 | mtdcr (memcfgd, tmp); | |
421 | mtdcr (memcfga, mem_mcopt1); | |
422 | tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; | |
423 | mtdcr (memcfga, mem_mcopt1); | |
424 | mtdcr (memcfgd, tmp); | |
425 | udelay (600); | |
426 | #ifdef SDRAM_DEBUG | |
427 | serial_puts ("fill the memory..\n"); | |
428 | #endif | |
429 | serial_puts ("."); | |
430 | /* now, fill all the memory */ | |
431 | tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz); | |
432 | p = (unsigned long) 0; | |
433 | while ((unsigned long) p < tmp) { | |
434 | *p++ = 0L; | |
435 | if (!((unsigned long) p % 0x00800000)) /* every 8MByte */ | |
436 | serial_puts ("."); | |
858b1a64 WD |
437 | } |
438 | /* enable bank 0 */ | |
439 | serial_puts ("."); | |
440 | #ifdef SDRAM_DEBUG | |
441 | serial_puts ("enable ECC\n"); | |
442 | #endif | |
443 | udelay (400); | |
444 | mtdcr (memcfga, mem_ecccf); | |
445 | tmp = mfdcr (memcfgd); | |
446 | tmp |= 0x00800000; /* enable bank 0 */ | |
447 | mtdcr (memcfgd, tmp); | |
448 | udelay (400); | |
449 | } else | |
450 | #endif | |
451 | { | |
452 | /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ | |
453 | mtdcr (memcfga, mem_mcopt1); | |
454 | tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000; | |
455 | mtdcr (memcfga, mem_mcopt1); | |
456 | mtdcr (memcfgd, tmp); | |
457 | udelay (400); | |
458 | } | |
459 | serial_puts ("\n"); | |
460 | return (0); | |
461 | } | |
462 | ||
463 | int board_pre_init (void) | |
464 | { | |
465 | init_sdram (); | |
466 | ||
467 | /*-------------------------------------------------------------------------+ | |
468 | | Interrupt controller setup for the PIP405 board. | |
469 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
470 | | IRQ 16 405GP internally generated; active low; level sensitive | |
471 | | IRQ 17-24 RESERVED | |
472 | | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive | |
473 | | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive | |
474 | | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive | |
475 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
476 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
477 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
478 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
479 | | Note for MIP405 board: | |
480 | | An interrupt taken for the SouthBridge (IRQ 25) indicates that | |
481 | | the Interrupt Controller in the South Bridge has caused the | |
482 | | interrupt. The IC must be read to determine which device | |
483 | | caused the interrupt. | |
484 | | | |
485 | +-------------------------------------------------------------------------*/ | |
486 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
487 | mtdcr (uicer, 0x00000000); /* disable all ints */ | |
488 | mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ | |
489 | mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ | |
490 | mtdcr (uictr, 0x10000000); /* set int trigger levels */ | |
491 | mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
492 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
493 | return 0; | |
494 | } | |
495 | ||
496 | ||
497 | /* | |
498 | * Get some PLD Registers | |
499 | */ | |
500 | ||
501 | unsigned short get_pld_parvers (void) | |
502 | { | |
503 | unsigned short result; | |
504 | unsigned char rc; | |
505 | ||
506 | rc = in8 (PLD_PART_REG); | |
507 | result = (unsigned short) rc << 8; | |
508 | rc = in8 (PLD_VERS_REG); | |
509 | result |= rc; | |
510 | return result; | |
511 | } | |
512 | ||
513 | ||
858b1a64 WD |
514 | void user_led0 (unsigned char on) |
515 | { | |
516 | if (on) | |
517 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4)); | |
518 | else | |
519 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb)); | |
520 | } | |
521 | ||
522 | ||
523 | void ide_set_reset (int idereset) | |
524 | { | |
525 | /* if reset = 1 IDE reset will be asserted */ | |
526 | if (idereset) | |
527 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1)); | |
528 | else { | |
529 | udelay (10000); | |
530 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe)); | |
531 | } | |
532 | } | |
533 | ||
534 | ||
535 | /* ------------------------------------------------------------------------- */ | |
536 | ||
f3e0de60 | 537 | void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var) |
858b1a64 | 538 | { |
f3e0de60 WD |
539 | #if !defined(CONFIG_MIP405T) |
540 | unsigned char bc,rc,tmp; | |
858b1a64 | 541 | int i; |
858b1a64 | 542 | |
f3e0de60 WD |
543 | bc = in8 (PLD_BOARD_CFG_REG); |
544 | tmp = ~bc; | |
545 | tmp &= 0xf; | |
858b1a64 WD |
546 | rc = 0; |
547 | for (i = 0; i < 4; i++) { | |
548 | rc <<= 1; | |
f3e0de60 WD |
549 | rc += (tmp & 0x1); |
550 | tmp >>= 1; | |
858b1a64 WD |
551 | } |
552 | rc++; | |
33149b88 WD |
553 | if((((bc>>4) & 0xf)==0x1) /* Rev B PCB with */ |
554 | && (rc==0x1)) /* Population Option 1 is a -3 */ | |
555 | rc=3; | |
f3e0de60 WD |
556 | *pcbrev=(bc >> 4) & 0xf; |
557 | *var=rc; | |
558 | #else | |
559 | unsigned char bc; | |
560 | bc = in8 (PLD_BOARD_CFG_REG); | |
561 | *pcbrev=(bc >> 4) & 0xf; | |
562 | *var=bc & 0xf ; | |
563 | #endif | |
564 | } | |
565 | ||
566 | /* | |
567 | * Check Board Identity: | |
568 | */ | |
569 | /* serial String: "MIP405_1000" OR "MIP405T_1000" */ | |
570 | #if !defined(CONFIG_MIP405T) | |
571 | #define BOARD_NAME "MIP405" | |
572 | #else | |
573 | #define BOARD_NAME "MIP405T" | |
574 | #endif | |
575 | ||
576 | int checkboard (void) | |
577 | { | |
578 | unsigned char s[50]; | |
579 | unsigned char bc, var; | |
580 | int i; | |
581 | backup_t *b = (backup_t *) s; | |
582 | ||
583 | puts ("Board: "); | |
584 | get_pcbrev_var(&bc,&var); | |
858b1a64 | 585 | i = getenv_r ("serial#", s, 32); |
f3e0de60 | 586 | if ((i == 0) || strncmp (s, BOARD_NAME,sizeof(BOARD_NAME))) { |
858b1a64 WD |
587 | get_backup_values (b); |
588 | if (strncmp (b->signature, "MPL\0", 4) != 0) { | |
f3e0de60 WD |
589 | puts ("### No HW ID - assuming " BOARD_NAME); |
590 | printf ("-%d Rev %c", var, 'A' + bc); | |
858b1a64 | 591 | } else { |
f3e0de60 WD |
592 | b->serial_name[sizeof(BOARD_NAME)-1] = 0; |
593 | printf ("%s-%d Rev %c SN: %s", b->serial_name, var, | |
594 | 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]); | |
858b1a64 WD |
595 | } |
596 | } else { | |
f3e0de60 WD |
597 | s[sizeof(BOARD_NAME)-1] = 0; |
598 | printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc, | |
599 | &s[sizeof(BOARD_NAME)]); | |
858b1a64 WD |
600 | } |
601 | bc = in8 (PLD_EXT_CONF_REG); | |
602 | printf (" Boot Config: 0x%x\n", bc); | |
603 | return (0); | |
604 | } | |
605 | ||
606 | ||
607 | /* ------------------------------------------------------------------------- */ | |
608 | /* ------------------------------------------------------------------------- */ | |
609 | /* | |
610 | initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of | |
611 | the necessary info for SDRAM controller configuration | |
612 | */ | |
613 | /* ------------------------------------------------------------------------- */ | |
614 | /* ------------------------------------------------------------------------- */ | |
615 | static int test_dram (unsigned long ramsize); | |
616 | ||
617 | long int initdram (int board_type) | |
618 | { | |
619 | ||
620 | unsigned long bank_reg[4], tmp, bank_size; | |
621 | int i, ds; | |
622 | unsigned long TotalSize; | |
623 | ||
624 | ds = 0; | |
625 | /* since the DRAM controller is allready set up, calculate the size with the | |
626 | bank registers */ | |
627 | mtdcr (memcfga, mem_mb0cf); | |
628 | bank_reg[0] = mfdcr (memcfgd); | |
629 | mtdcr (memcfga, mem_mb1cf); | |
630 | bank_reg[1] = mfdcr (memcfgd); | |
631 | mtdcr (memcfga, mem_mb2cf); | |
632 | bank_reg[2] = mfdcr (memcfgd); | |
633 | mtdcr (memcfga, mem_mb3cf); | |
634 | bank_reg[3] = mfdcr (memcfgd); | |
635 | TotalSize = 0; | |
636 | for (i = 0; i < 4; i++) { | |
637 | if ((bank_reg[i] & 0x1) == 0x1) { | |
638 | tmp = (bank_reg[i] >> 17) & 0x7; | |
639 | bank_size = 4 << tmp; | |
640 | TotalSize += bank_size; | |
641 | } else | |
642 | ds = 1; | |
643 | } | |
644 | mtdcr (memcfga, mem_ecccf); | |
645 | tmp = mfdcr (memcfgd); | |
646 | ||
647 | if (!tmp) | |
648 | printf ("No "); | |
649 | printf ("ECC "); | |
650 | ||
651 | test_dram (TotalSize * MEGA_BYTE); | |
652 | return (TotalSize * MEGA_BYTE); | |
653 | } | |
654 | ||
655 | /* ------------------------------------------------------------------------- */ | |
656 | ||
657 | extern int mem_test (unsigned long start, unsigned long ramsize, | |
658 | int quiet); | |
659 | ||
660 | static int test_dram (unsigned long ramsize) | |
661 | { | |
662 | #ifdef SDRAM_DEBUG | |
663 | mem_test (0L, ramsize, 1); | |
664 | #endif | |
665 | /* not yet implemented */ | |
666 | return (1); | |
667 | } | |
668 | ||
669 | int misc_init_r (void) | |
670 | { | |
f3e0de60 WD |
671 | /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ |
672 | if (mfdcr(strap) & PSR_ROM_LOC) | |
673 | mtspr(ccr0, (mfspr(ccr0) & ~0x80)); | |
674 | ||
858b1a64 WD |
675 | return (0); |
676 | } | |
677 | ||
678 | ||
679 | void print_mip405_rev (void) | |
680 | { | |
f3e0de60 WD |
681 | unsigned char part, vers, pcbrev, var; |
682 | ||
683 | get_pcbrev_var(&pcbrev,&var); | |
858b1a64 WD |
684 | part = in8 (PLD_PART_REG); |
685 | vers = in8 (PLD_VERS_REG); | |
f3e0de60 WD |
686 | printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n", |
687 | var, pcbrev + 'A', part & 0x7F, vers); | |
858b1a64 WD |
688 | } |
689 | ||
33149b88 | 690 | extern void mem_test_reloc(void); |
858b1a64 WD |
691 | |
692 | int last_stage_init (void) | |
693 | { | |
33149b88 | 694 | mem_test_reloc(); |
3e38691e | 695 | /* write correct LED configuration */ |
858b1a64 WD |
696 | if (miiphy_write (0x1, 0x14, 0x2402) != 0) { |
697 | printf ("Error writing to the PHY\n"); | |
698 | } | |
3e38691e WD |
699 | /* since LED/CFG2 is not connected on the -2, |
700 | * write to correct capability information */ | |
701 | if (miiphy_write (0x1, 0x4, 0x01E1) != 0) { | |
702 | printf ("Error writing to the PHY\n"); | |
703 | } | |
858b1a64 WD |
704 | print_mip405_rev (); |
705 | show_stdio_dev (); | |
706 | check_env (); | |
707 | return 0; | |
708 | } | |
709 | ||
710 | /*************************************************************************** | |
711 | * some helping routines | |
712 | */ | |
713 | ||
714 | int overwrite_console (void) | |
715 | { | |
716 | return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */ | |
717 | } | |
718 | ||
719 | ||
720 | /************************************************************************ | |
721 | * Print MIP405 Info | |
722 | ************************************************************************/ | |
723 | void print_mip405_info (void) | |
724 | { | |
725 | unsigned char part, vers, cfg, irq_reg, com_mode, ext; | |
726 | ||
727 | part = in8 (PLD_PART_REG); | |
728 | vers = in8 (PLD_VERS_REG); | |
729 | cfg = in8 (PLD_BOARD_CFG_REG); | |
730 | irq_reg = in8 (PLD_IRQ_REG); | |
731 | com_mode = in8 (PLD_COM_MODE_REG); | |
732 | ext = in8 (PLD_EXT_CONF_REG); | |
733 | ||
f3e0de60 | 734 | printf ("PLD Part %d version %d\n", part & 0x7F, vers); |
858b1a64 WD |
735 | printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A'); |
736 | printf ("Population Options %d %d %d %d\n", (cfg) & 0x1, | |
737 | (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1); | |
738 | printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off"); | |
739 | printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3); | |
f3e0de60 | 740 | #if !defined(CONFIG_MIP405T) |
858b1a64 WD |
741 | printf ("User Config Switch %d %d %d %d %d %d %d %d\n", |
742 | (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, | |
743 | (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, | |
744 | (ext >> 6) & 0x1, (ext >> 7) & 0x1); | |
745 | printf ("SER1 uses handshakes %s\n", | |
746 | (ext & 0x80) ? "DTR/DSR" : "RTS/CTS"); | |
f3e0de60 WD |
747 | #else |
748 | printf ("User Config Switch %d %d %d %d %d %d %d %d %d\n", | |
749 | (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, | |
750 | (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, | |
751 | (ext >> 6) & 0x1,(ext >> 7) & 0x1,(ext >> 8) & 0x1); | |
752 | #endif | |
858b1a64 WD |
753 | printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted"); |
754 | printf ("IRQs:\n"); | |
755 | printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active"); | |
f3e0de60 | 756 | #if !defined(CONFIG_MIP405T) |
858b1a64 WD |
757 | printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active"); |
758 | printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active"); | |
f3e0de60 | 759 | #endif |
858b1a64 WD |
760 | printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active"); |
761 | printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); | |
762 | printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); | |
763 | } |