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858b1a64 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * | |
24 | * TODO: clean-up | |
25 | */ | |
26 | ||
27 | /* | |
28 | * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? | |
29 | * | |
30 | * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being | |
31 | * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum | |
32 | * parameters from the datasheet are: | |
33 | * Tclk = 7.5ns (CL = 2) | |
34 | * Trp = 15ns | |
35 | * Trc = 60ns | |
36 | * Trcd = 15ns | |
37 | * Trfc = 66ns | |
38 | * | |
39 | * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock | |
40 | * period is 10ns and the parameters needed for the Timing Register are: | |
41 | * CASL = CL = 2 clock cycles | |
42 | * PTA = Trp = 15ns / 10ns = 2 clock cycles | |
43 | * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles | |
44 | * LDF = 2 clock cycles (but can be extended to meet board-level timing) | |
45 | * RFTA = Trfc = 66ns / 10ns= 7 clock cycles | |
46 | * RCD = Trcd = 15ns / 10ns= 2 clock cycles | |
47 | * | |
48 | * The actual bit settings in the register would be: | |
49 | * | |
50 | * CASL = 0b01 | |
51 | * PTA = 0b01 | |
52 | * CTP = 0b10 | |
53 | * LDF = 0b01 | |
54 | * RFTA = 0b011 | |
55 | * RCD = 0b01 | |
56 | * | |
57 | * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc | |
58 | * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay | |
59 | * defined as Trc rather than Trfc. | |
60 | * When using DIMM modules, most but not all of the required timing parameters can be read | |
61 | * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc | |
62 | * are not available from the EEPROM | |
63 | */ | |
64 | ||
65 | #include <common.h> | |
66 | #include "mip405.h" | |
67 | #include <asm/processor.h> | |
79b2d0bb | 68 | #include <4xx_i2c.h> |
858b1a64 WD |
69 | #include <miiphy.h> |
70 | #include "../common/common_util.h" | |
28c34504 | 71 | #include <stdio_dev.h> |
858b1a64 | 72 | #include <i2c.h> |
27b207fd | 73 | #include <rtc.h> |
d87080b7 WD |
74 | |
75 | DECLARE_GLOBAL_DATA_PTR; | |
76 | ||
858b1a64 | 77 | #undef SDRAM_DEBUG |
f3e0de60 | 78 | #define ENABLE_ECC /* for ecc boards */ |
858b1a64 WD |
79 | #define FALSE 0 |
80 | #define TRUE 1 | |
81 | ||
82 | /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ | |
83 | #ifndef __ldiv_t_defined | |
84 | typedef struct { | |
85 | long int quot; /* Quotient */ | |
86 | long int rem; /* Remainder */ | |
87 | } ldiv_t; | |
88 | extern ldiv_t ldiv (long int __numer, long int __denom); | |
89 | # define __ldiv_t_defined 1 | |
90 | #endif | |
91 | ||
92 | ||
53677ef1 WD |
93 | #define PLD_PART_REG PER_PLD_ADDR + 0 |
94 | #define PLD_VERS_REG PER_PLD_ADDR + 1 | |
95 | #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 | |
96 | #define PLD_IRQ_REG PER_PLD_ADDR + 3 | |
97 | #define PLD_COM_MODE_REG PER_PLD_ADDR + 4 | |
98 | #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 | |
858b1a64 WD |
99 | |
100 | #define MEGA_BYTE (1024*1024) | |
101 | ||
102 | typedef struct { | |
103 | unsigned char boardtype; /* Board revision and Population Options */ | |
104 | unsigned char cal; /* cas Latency (will be programmend as cal-1) */ | |
105 | unsigned char trp; /* datain27 in clocks */ | |
106 | unsigned char trcd; /* datain29 in clocks */ | |
107 | unsigned char tras; /* datain30 in clocks */ | |
108 | unsigned char tctp; /* tras - trcd in clocks */ | |
109 | unsigned char am; /* Address Mod (will be programmed as am-1) */ | |
110 | unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */ | |
111 | unsigned char ecc; /* if true, ecc is enabled */ | |
112 | } sdram_t; | |
f3e0de60 WD |
113 | #if defined(CONFIG_MIP405T) |
114 | const sdram_t sdram_table[] = { | |
27b207fd | 115 | { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */ |
f3e0de60 WD |
116 | 3, /* Case Latenty = 3 */ |
117 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
118 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
119 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
120 | 4, /* tcpt 44 - 20ns = 24ns */ | |
27b207fd WD |
121 | 2, /* Address Mode = 2 (12x9x4) */ |
122 | 3, /* size value (32MByte) */ | |
f3e0de60 WD |
123 | 0}, /* ECC disabled */ |
124 | { 0xff, /* terminator */ | |
125 | 0xff, | |
126 | 0xff, | |
127 | 0xff, | |
128 | 0xff, | |
129 | 0xff, | |
130 | 0xff, | |
131 | 0xff } | |
132 | }; | |
133 | #else | |
858b1a64 WD |
134 | const sdram_t sdram_table[] = { |
135 | { 0x0f, /* Rev A, 128MByte -1 Board */ | |
136 | 3, /* Case Latenty = 3 */ | |
137 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
138 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
139 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
858b1a64 | 140 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 | 141 | 3, /* Address Mode = 3 */ |
858b1a64 WD |
142 | 5, /* size value */ |
143 | 1}, /* ECC enabled */ | |
144 | { 0x07, /* Rev A, 64MByte -2 Board */ | |
145 | 3, /* Case Latenty = 3 */ | |
146 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
147 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
148 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
858b1a64 | 149 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 | 150 | 2, /* Address Mode = 2 */ |
858b1a64 WD |
151 | 4, /* size value */ |
152 | 1}, /* ECC enabled */ | |
3e38691e WD |
153 | { 0x03, /* Rev A, 128MByte -4 Board */ |
154 | 3, /* Case Latenty = 3 */ | |
155 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
33149b88 WD |
156 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ |
157 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
3e38691e | 158 | 4, /* tcpt 44 - 20ns = 24ns */ |
33149b88 WD |
159 | 3, /* Address Mode = 3 */ |
160 | 5, /* size value */ | |
161 | 1}, /* ECC enabled */ | |
162 | { 0x1f, /* Rev B, 128MByte -3 Board */ | |
163 | 3, /* Case Latenty = 3 */ | |
164 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
165 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
166 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
167 | 4, /* tcpt 44 - 20ns = 24ns */ | |
168 | 3, /* Address Mode = 3 */ | |
3e38691e WD |
169 | 5, /* size value */ |
170 | 1}, /* ECC enabled */ | |
4a551709 WD |
171 | { 0x2f, /* Rev C, 128MByte -3 Board */ |
172 | 3, /* Case Latenty = 3 */ | |
173 | 3, /* trp 20ns / 7.5 ns datain[27] */ | |
174 | 3, /* trcd 20ns /7.5 ns (datain[29]) */ | |
175 | 6, /* tras 44ns /7.5 ns (datain[30]) */ | |
176 | 4, /* tcpt 44 - 20ns = 24ns */ | |
177 | 3, /* Address Mode = 3 */ | |
178 | 5, /* size value */ | |
179 | 1}, /* ECC enabled */ | |
858b1a64 WD |
180 | { 0xff, /* terminator */ |
181 | 0xff, | |
182 | 0xff, | |
183 | 0xff, | |
184 | 0xff, | |
185 | 0xff, | |
186 | 0xff, | |
187 | 0xff } | |
188 | }; | |
f3e0de60 | 189 | #endif /*CONFIG_MIP405T */ |
858b1a64 WD |
190 | void SDRAM_err (const char *s) |
191 | { | |
192 | #ifndef SDRAM_DEBUG | |
858b1a64 WD |
193 | (void) get_clocks (); |
194 | gd->baudrate = 9600; | |
195 | serial_init (); | |
196 | #endif | |
197 | serial_puts ("\n"); | |
198 | serial_puts (s); | |
199 | serial_puts ("\n enable SDRAM_DEBUG for more info\n"); | |
200 | for (;;); | |
201 | } | |
202 | ||
203 | ||
204 | unsigned char get_board_revcfg (void) | |
205 | { | |
206 | out8 (PER_BOARD_ADDR, 0); | |
207 | return (in8 (PER_BOARD_ADDR)); | |
208 | } | |
209 | ||
210 | ||
211 | #ifdef SDRAM_DEBUG | |
212 | ||
213 | void write_hex (unsigned char i) | |
214 | { | |
215 | char cc; | |
216 | ||
217 | cc = i >> 4; | |
218 | cc &= 0xf; | |
219 | if (cc > 9) | |
220 | serial_putc (cc + 55); | |
221 | else | |
222 | serial_putc (cc + 48); | |
223 | cc = i & 0xf; | |
224 | if (cc > 9) | |
225 | serial_putc (cc + 55); | |
226 | else | |
227 | serial_putc (cc + 48); | |
228 | } | |
229 | ||
230 | void write_4hex (unsigned long val) | |
231 | { | |
232 | write_hex ((unsigned char) (val >> 24)); | |
233 | write_hex ((unsigned char) (val >> 16)); | |
234 | write_hex ((unsigned char) (val >> 8)); | |
235 | write_hex ((unsigned char) val); | |
236 | } | |
237 | ||
238 | #endif | |
239 | ||
240 | ||
241 | int init_sdram (void) | |
242 | { | |
858b1a64 WD |
243 | unsigned long tmp, baseaddr; |
244 | unsigned short i; | |
245 | unsigned char trp_clocks, | |
246 | trcd_clocks, | |
247 | tras_clocks, | |
248 | trc_clocks, | |
249 | tctp_clocks; | |
250 | unsigned char cal_val; | |
251 | unsigned char bc; | |
f3e0de60 | 252 | unsigned long sdram_tim, sdram_bank; |
858b1a64 | 253 | |
6d0f6bcf | 254 | /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/ |
858b1a64 WD |
255 | (void) get_clocks (); |
256 | gd->baudrate = 9600; | |
257 | serial_init (); | |
f3e0de60 | 258 | /* set up the pld */ |
d1c3b275 SR |
259 | mtdcr (EBC0_CFGADDR, PB7AP); |
260 | mtdcr (EBC0_CFGDATA, PLD_AP); | |
261 | mtdcr (EBC0_CFGADDR, PB7CR); | |
262 | mtdcr (EBC0_CFGDATA, PLD_CR); | |
f3e0de60 WD |
263 | /* THIS IS OBSOLETE */ |
264 | /* set up the board rev reg*/ | |
d1c3b275 SR |
265 | mtdcr (EBC0_CFGADDR, PB5AP); |
266 | mtdcr (EBC0_CFGDATA, BOARD_AP); | |
267 | mtdcr (EBC0_CFGADDR, PB5CR); | |
268 | mtdcr (EBC0_CFGDATA, BOARD_CR); | |
f3e0de60 WD |
269 | #ifdef SDRAM_DEBUG |
270 | /* get all informations from PLD */ | |
271 | serial_puts ("\nPLD Part 0x"); | |
272 | bc = in8 (PLD_PART_REG); | |
273 | write_hex (bc); | |
274 | serial_puts ("\nPLD Vers 0x"); | |
275 | bc = in8 (PLD_VERS_REG); | |
276 | write_hex (bc); | |
277 | serial_puts ("\nBoard Rev 0x"); | |
278 | bc = in8 (PLD_BOARD_CFG_REG); | |
279 | write_hex (bc); | |
280 | serial_puts ("\n"); | |
281 | #endif | |
282 | /* check board */ | |
283 | bc = in8 (PLD_PART_REG); | |
284 | #if defined(CONFIG_MIP405T) | |
285 | if((bc & 0x80)==0) | |
286 | SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n"); | |
287 | #else | |
288 | if((bc & 0x80)==0x80) | |
289 | SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); | |
290 | #endif | |
f3e0de60 | 291 | /* set-up the chipselect machine */ |
d1c3b275 SR |
292 | mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */ |
293 | tmp = mfdcr (EBC0_CFGDATA); | |
f3e0de60 | 294 | if ((tmp & 0x00002000) == 0) { |
858b1a64 | 295 | /* MPS Boot, set up the flash */ |
d1c3b275 SR |
296 | mtdcr (EBC0_CFGADDR, PB1AP); |
297 | mtdcr (EBC0_CFGDATA, FLASH_AP); | |
298 | mtdcr (EBC0_CFGADDR, PB1CR); | |
299 | mtdcr (EBC0_CFGDATA, FLASH_CR); | |
858b1a64 WD |
300 | } else { |
301 | /* Flash boot, set up the MPS */ | |
d1c3b275 SR |
302 | mtdcr (EBC0_CFGADDR, PB1AP); |
303 | mtdcr (EBC0_CFGDATA, MPS_AP); | |
304 | mtdcr (EBC0_CFGADDR, PB1CR); | |
305 | mtdcr (EBC0_CFGDATA, MPS_CR); | |
858b1a64 WD |
306 | } |
307 | /* set up UART0 (CS2) and UART1 (CS3) */ | |
d1c3b275 SR |
308 | mtdcr (EBC0_CFGADDR, PB2AP); |
309 | mtdcr (EBC0_CFGDATA, UART0_AP); | |
310 | mtdcr (EBC0_CFGADDR, PB2CR); | |
311 | mtdcr (EBC0_CFGDATA, UART0_CR); | |
312 | mtdcr (EBC0_CFGADDR, PB3AP); | |
313 | mtdcr (EBC0_CFGDATA, UART1_AP); | |
314 | mtdcr (EBC0_CFGADDR, PB3CR); | |
315 | mtdcr (EBC0_CFGDATA, UART1_CR); | |
f3e0de60 | 316 | bc = in8 (PLD_BOARD_CFG_REG); |
858b1a64 WD |
317 | #ifdef SDRAM_DEBUG |
318 | serial_puts ("\nstart SDRAM Setup\n"); | |
319 | serial_puts ("\nBoard Rev: "); | |
320 | write_hex (bc); | |
321 | serial_puts ("\n"); | |
322 | #endif | |
323 | i = 0; | |
6d0f6bcf | 324 | baseaddr = CONFIG_SYS_SDRAM_BASE; |
858b1a64 WD |
325 | while (sdram_table[i].sz != 0xff) { |
326 | if (sdram_table[i].boardtype == bc) | |
327 | break; | |
328 | i++; | |
329 | } | |
330 | if (sdram_table[i].boardtype != bc) | |
331 | SDRAM_err ("No SDRAM table found for this board!!!\n"); | |
332 | #ifdef SDRAM_DEBUG | |
333 | serial_puts (" found table "); | |
334 | write_hex (i); | |
335 | serial_puts (" \n"); | |
336 | #endif | |
27b207fd WD |
337 | /* since the ECC initialisation needs some time, |
338 | * we show that we're alive | |
339 | */ | |
340 | if (sdram_table[i].ecc) | |
341 | serial_puts ("\nInitializing SDRAM, Please stand by"); | |
858b1a64 WD |
342 | cal_val = sdram_table[i].cal - 1; /* Cas Latency */ |
343 | trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */ | |
344 | trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ | |
345 | tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ | |
346 | /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ | |
347 | tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */ | |
348 | /* trc_clocks is sum of trp_clocks + tras_clocks */ | |
349 | trc_clocks = trp_clocks + tras_clocks; | |
350 | /* get SDRAM timing register */ | |
d1c3b275 SR |
351 | mtdcr (SDRAM0_CFGADDR, mem_sdtr1); |
352 | sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; | |
858b1a64 WD |
353 | /* insert CASL value */ |
354 | sdram_tim |= ((unsigned long) (cal_val)) << 23; | |
355 | /* insert PTA value */ | |
356 | sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18; | |
357 | /* insert CTP value */ | |
358 | sdram_tim |= | |
359 | ((unsigned long) (trc_clocks - trp_clocks - | |
360 | trcd_clocks)) << 16; | |
361 | /* insert LDF (always 01) */ | |
362 | sdram_tim |= ((unsigned long) 0x01) << 14; | |
363 | /* insert RFTA value */ | |
364 | sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2; | |
365 | /* insert RCD value */ | |
366 | sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0; | |
367 | ||
368 | tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */ | |
369 | /* insert SZ value; */ | |
370 | tmp |= ((unsigned long) sdram_table[i].sz << 17); | |
371 | /* get SDRAM bank 0 register */ | |
d1c3b275 SR |
372 | mtdcr (SDRAM0_CFGADDR, mem_mb0cf); |
373 | sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; | |
858b1a64 WD |
374 | sdram_bank |= (baseaddr | tmp | 0x01); |
375 | ||
376 | #ifdef SDRAM_DEBUG | |
377 | serial_puts ("sdtr: "); | |
378 | write_4hex (sdram_tim); | |
379 | serial_puts ("\n"); | |
380 | #endif | |
381 | ||
382 | /* write SDRAM timing register */ | |
d1c3b275 SR |
383 | mtdcr (SDRAM0_CFGADDR, mem_sdtr1); |
384 | mtdcr (SDRAM0_CFGDATA, sdram_tim); | |
858b1a64 WD |
385 | |
386 | #ifdef SDRAM_DEBUG | |
387 | serial_puts ("mb0cf: "); | |
388 | write_4hex (sdram_bank); | |
389 | serial_puts ("\n"); | |
390 | #endif | |
391 | ||
392 | /* write SDRAM bank 0 register */ | |
d1c3b275 SR |
393 | mtdcr (SDRAM0_CFGADDR, mem_mb0cf); |
394 | mtdcr (SDRAM0_CFGDATA, sdram_bank); | |
858b1a64 WD |
395 | |
396 | if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ | |
397 | /* get SDRAM refresh interval register */ | |
d1c3b275 SR |
398 | mtdcr (SDRAM0_CFGADDR, mem_rtr); |
399 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; | |
858b1a64 WD |
400 | tmp |= 0x07F00000; |
401 | } else { | |
402 | /* get SDRAM refresh interval register */ | |
d1c3b275 SR |
403 | mtdcr (SDRAM0_CFGADDR, mem_rtr); |
404 | tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; | |
858b1a64 WD |
405 | tmp |= 0x05F00000; |
406 | } | |
407 | /* write SDRAM refresh interval register */ | |
d1c3b275 SR |
408 | mtdcr (SDRAM0_CFGADDR, mem_rtr); |
409 | mtdcr (SDRAM0_CFGDATA, tmp); | |
858b1a64 | 410 | /* enable ECC if used */ |
f3e0de60 | 411 | #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) |
858b1a64 WD |
412 | if (sdram_table[i].ecc) { |
413 | /* disable checking for all banks */ | |
f3e0de60 | 414 | unsigned long *p; |
858b1a64 WD |
415 | #ifdef SDRAM_DEBUG |
416 | serial_puts ("disable ECC.. "); | |
417 | #endif | |
d1c3b275 SR |
418 | mtdcr (SDRAM0_CFGADDR, mem_ecccf); |
419 | tmp = mfdcr (SDRAM0_CFGDATA); | |
858b1a64 | 420 | tmp &= 0xff0fffff; /* disable all banks */ |
d1c3b275 | 421 | mtdcr (SDRAM0_CFGADDR, mem_ecccf); |
858b1a64 WD |
422 | /* set up SDRAM Controller with ECC enabled */ |
423 | #ifdef SDRAM_DEBUG | |
424 | serial_puts ("setup SDRAM Controller.. "); | |
425 | #endif | |
d1c3b275 SR |
426 | mtdcr (SDRAM0_CFGDATA, tmp); |
427 | mtdcr (SDRAM0_CFGADDR, mem_mcopt1); | |
428 | tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; | |
429 | mtdcr (SDRAM0_CFGADDR, mem_mcopt1); | |
430 | mtdcr (SDRAM0_CFGDATA, tmp); | |
858b1a64 WD |
431 | udelay (600); |
432 | #ifdef SDRAM_DEBUG | |
433 | serial_puts ("fill the memory..\n"); | |
434 | #endif | |
435 | serial_puts ("."); | |
436 | /* now, fill all the memory */ | |
437 | tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz); | |
438 | p = (unsigned long) 0; | |
439 | while ((unsigned long) p < tmp) { | |
440 | *p++ = 0L; | |
441 | if (!((unsigned long) p % 0x00800000)) /* every 8MByte */ | |
442 | serial_puts ("."); | |
858b1a64 WD |
443 | } |
444 | /* enable bank 0 */ | |
445 | serial_puts ("."); | |
446 | #ifdef SDRAM_DEBUG | |
447 | serial_puts ("enable ECC\n"); | |
448 | #endif | |
449 | udelay (400); | |
d1c3b275 SR |
450 | mtdcr (SDRAM0_CFGADDR, mem_ecccf); |
451 | tmp = mfdcr (SDRAM0_CFGDATA); | |
858b1a64 | 452 | tmp |= 0x00800000; /* enable bank 0 */ |
d1c3b275 | 453 | mtdcr (SDRAM0_CFGDATA, tmp); |
858b1a64 WD |
454 | udelay (400); |
455 | } else | |
456 | #endif | |
457 | { | |
458 | /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ | |
d1c3b275 SR |
459 | mtdcr (SDRAM0_CFGADDR, mem_mcopt1); |
460 | tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; | |
461 | mtdcr (SDRAM0_CFGADDR, mem_mcopt1); | |
462 | mtdcr (SDRAM0_CFGDATA, tmp); | |
858b1a64 WD |
463 | udelay (400); |
464 | } | |
465 | serial_puts ("\n"); | |
466 | return (0); | |
467 | } | |
468 | ||
c837dcb1 | 469 | int board_early_init_f (void) |
858b1a64 WD |
470 | { |
471 | init_sdram (); | |
472 | ||
473 | /*-------------------------------------------------------------------------+ | |
474 | | Interrupt controller setup for the PIP405 board. | |
475 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
476 | | IRQ 16 405GP internally generated; active low; level sensitive | |
477 | | IRQ 17-24 RESERVED | |
478 | | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive | |
479 | | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive | |
480 | | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive | |
481 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
482 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
483 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
484 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
485 | | Note for MIP405 board: | |
486 | | An interrupt taken for the SouthBridge (IRQ 25) indicates that | |
487 | | the Interrupt Controller in the South Bridge has caused the | |
488 | | interrupt. The IC must be read to determine which device | |
489 | | caused the interrupt. | |
490 | | | |
491 | +-------------------------------------------------------------------------*/ | |
492 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
493 | mtdcr (uicer, 0x00000000); /* disable all ints */ | |
494 | mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ | |
495 | mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ | |
496 | mtdcr (uictr, 0x10000000); /* set int trigger levels */ | |
497 | mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
498 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
499 | return 0; | |
500 | } | |
501 | ||
502 | ||
503 | /* | |
504 | * Get some PLD Registers | |
505 | */ | |
506 | ||
507 | unsigned short get_pld_parvers (void) | |
508 | { | |
509 | unsigned short result; | |
510 | unsigned char rc; | |
511 | ||
512 | rc = in8 (PLD_PART_REG); | |
513 | result = (unsigned short) rc << 8; | |
514 | rc = in8 (PLD_VERS_REG); | |
515 | result |= rc; | |
516 | return result; | |
517 | } | |
518 | ||
519 | ||
858b1a64 WD |
520 | void user_led0 (unsigned char on) |
521 | { | |
522 | if (on) | |
523 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4)); | |
524 | else | |
525 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb)); | |
526 | } | |
527 | ||
528 | ||
529 | void ide_set_reset (int idereset) | |
530 | { | |
531 | /* if reset = 1 IDE reset will be asserted */ | |
532 | if (idereset) | |
533 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1)); | |
534 | else { | |
535 | udelay (10000); | |
536 | out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe)); | |
537 | } | |
538 | } | |
539 | ||
540 | ||
541 | /* ------------------------------------------------------------------------- */ | |
542 | ||
f3e0de60 | 543 | void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var) |
858b1a64 | 544 | { |
f3e0de60 WD |
545 | #if !defined(CONFIG_MIP405T) |
546 | unsigned char bc,rc,tmp; | |
858b1a64 | 547 | int i; |
858b1a64 | 548 | |
f3e0de60 WD |
549 | bc = in8 (PLD_BOARD_CFG_REG); |
550 | tmp = ~bc; | |
551 | tmp &= 0xf; | |
858b1a64 WD |
552 | rc = 0; |
553 | for (i = 0; i < 4; i++) { | |
554 | rc <<= 1; | |
f3e0de60 WD |
555 | rc += (tmp & 0x1); |
556 | tmp >>= 1; | |
858b1a64 WD |
557 | } |
558 | rc++; | |
4a551709 WD |
559 | if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */ |
560 | || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */ | |
33149b88 WD |
561 | && (rc==0x1)) /* Population Option 1 is a -3 */ |
562 | rc=3; | |
f3e0de60 WD |
563 | *pcbrev=(bc >> 4) & 0xf; |
564 | *var=rc; | |
565 | #else | |
566 | unsigned char bc; | |
567 | bc = in8 (PLD_BOARD_CFG_REG); | |
568 | *pcbrev=(bc >> 4) & 0xf; | |
27b207fd | 569 | *var=16-(bc & 0xf); |
f3e0de60 WD |
570 | #endif |
571 | } | |
572 | ||
573 | /* | |
574 | * Check Board Identity: | |
575 | */ | |
576 | /* serial String: "MIP405_1000" OR "MIP405T_1000" */ | |
577 | #if !defined(CONFIG_MIP405T) | |
578 | #define BOARD_NAME "MIP405" | |
579 | #else | |
580 | #define BOARD_NAME "MIP405T" | |
581 | #endif | |
582 | ||
583 | int checkboard (void) | |
584 | { | |
77ddac94 | 585 | char s[50]; |
f3e0de60 WD |
586 | unsigned char bc, var; |
587 | int i; | |
588 | backup_t *b = (backup_t *) s; | |
589 | ||
590 | puts ("Board: "); | |
591 | get_pcbrev_var(&bc,&var); | |
77ddac94 WD |
592 | i = getenv_r ("serial#", (char *)s, 32); |
593 | if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) { | |
858b1a64 WD |
594 | get_backup_values (b); |
595 | if (strncmp (b->signature, "MPL\0", 4) != 0) { | |
f3e0de60 WD |
596 | puts ("### No HW ID - assuming " BOARD_NAME); |
597 | printf ("-%d Rev %c", var, 'A' + bc); | |
858b1a64 | 598 | } else { |
f3e0de60 WD |
599 | b->serial_name[sizeof(BOARD_NAME)-1] = 0; |
600 | printf ("%s-%d Rev %c SN: %s", b->serial_name, var, | |
601 | 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]); | |
858b1a64 WD |
602 | } |
603 | } else { | |
f3e0de60 WD |
604 | s[sizeof(BOARD_NAME)-1] = 0; |
605 | printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc, | |
606 | &s[sizeof(BOARD_NAME)]); | |
858b1a64 WD |
607 | } |
608 | bc = in8 (PLD_EXT_CONF_REG); | |
609 | printf (" Boot Config: 0x%x\n", bc); | |
610 | return (0); | |
611 | } | |
612 | ||
613 | ||
614 | /* ------------------------------------------------------------------------- */ | |
615 | /* ------------------------------------------------------------------------- */ | |
616 | /* | |
617 | initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of | |
618 | the necessary info for SDRAM controller configuration | |
619 | */ | |
620 | /* ------------------------------------------------------------------------- */ | |
621 | /* ------------------------------------------------------------------------- */ | |
622 | static int test_dram (unsigned long ramsize); | |
623 | ||
9973e3c6 | 624 | phys_size_t initdram (int board_type) |
858b1a64 WD |
625 | { |
626 | ||
627 | unsigned long bank_reg[4], tmp, bank_size; | |
628 | int i, ds; | |
629 | unsigned long TotalSize; | |
630 | ||
631 | ds = 0; | |
632 | /* since the DRAM controller is allready set up, calculate the size with the | |
633 | bank registers */ | |
d1c3b275 SR |
634 | mtdcr (SDRAM0_CFGADDR, mem_mb0cf); |
635 | bank_reg[0] = mfdcr (SDRAM0_CFGDATA); | |
636 | mtdcr (SDRAM0_CFGADDR, mem_mb1cf); | |
637 | bank_reg[1] = mfdcr (SDRAM0_CFGDATA); | |
638 | mtdcr (SDRAM0_CFGADDR, mem_mb2cf); | |
639 | bank_reg[2] = mfdcr (SDRAM0_CFGDATA); | |
640 | mtdcr (SDRAM0_CFGADDR, mem_mb3cf); | |
641 | bank_reg[3] = mfdcr (SDRAM0_CFGDATA); | |
858b1a64 WD |
642 | TotalSize = 0; |
643 | for (i = 0; i < 4; i++) { | |
644 | if ((bank_reg[i] & 0x1) == 0x1) { | |
645 | tmp = (bank_reg[i] >> 17) & 0x7; | |
646 | bank_size = 4 << tmp; | |
647 | TotalSize += bank_size; | |
648 | } else | |
649 | ds = 1; | |
650 | } | |
d1c3b275 SR |
651 | mtdcr (SDRAM0_CFGADDR, mem_ecccf); |
652 | tmp = mfdcr (SDRAM0_CFGDATA); | |
858b1a64 WD |
653 | |
654 | if (!tmp) | |
655 | printf ("No "); | |
656 | printf ("ECC "); | |
657 | ||
658 | test_dram (TotalSize * MEGA_BYTE); | |
659 | return (TotalSize * MEGA_BYTE); | |
660 | } | |
661 | ||
662 | /* ------------------------------------------------------------------------- */ | |
663 | ||
858b1a64 WD |
664 | |
665 | static int test_dram (unsigned long ramsize) | |
666 | { | |
667 | #ifdef SDRAM_DEBUG | |
668 | mem_test (0L, ramsize, 1); | |
669 | #endif | |
670 | /* not yet implemented */ | |
671 | return (1); | |
672 | } | |
673 | ||
27b207fd WD |
674 | /* used to check if the time in RTC is valid */ |
675 | static unsigned long start; | |
676 | static struct rtc_time tm; | |
7205e407 | 677 | extern flash_info_t flash_info[]; /* info for FLASH chips */ |
27b207fd | 678 | |
858b1a64 WD |
679 | int misc_init_r (void) |
680 | { | |
7205e407 WD |
681 | /* adjust flash start and size as well as the offset */ |
682 | gd->bd->bi_flashstart=0-flash_info[0].size; | |
6d0f6bcf | 683 | gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; |
7205e407 WD |
684 | gd->bd->bi_flashoffset=0; |
685 | ||
27b207fd WD |
686 | /* check, if RTC is running */ |
687 | rtc_get (&tm); | |
688 | start=get_timer(0); | |
f3e0de60 | 689 | /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ |
d1c3b275 | 690 | if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) |
58ea142f | 691 | mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); |
f3e0de60 | 692 | |
858b1a64 WD |
693 | return (0); |
694 | } | |
695 | ||
696 | ||
697 | void print_mip405_rev (void) | |
698 | { | |
f3e0de60 WD |
699 | unsigned char part, vers, pcbrev, var; |
700 | ||
701 | get_pcbrev_var(&pcbrev,&var); | |
858b1a64 WD |
702 | part = in8 (PLD_PART_REG); |
703 | vers = in8 (PLD_VERS_REG); | |
f3e0de60 WD |
704 | printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n", |
705 | var, pcbrev + 'A', part & 0x7F, vers); | |
858b1a64 WD |
706 | } |
707 | ||
63e73c9a WD |
708 | |
709 | #ifdef CONFIG_POST | |
710 | /* | |
711 | * Returns 1 if keys pressed to start the power-on long-running tests | |
712 | * Called from board_init_f(). | |
713 | */ | |
714 | int post_hotkeys_pressed(void) | |
715 | { | |
716 | return 0; /* No hotkeys supported */ | |
717 | } | |
718 | #endif | |
719 | ||
33149b88 | 720 | extern void mem_test_reloc(void); |
27b207fd | 721 | extern int mk_date (char *, struct rtc_time *); |
858b1a64 WD |
722 | |
723 | int last_stage_init (void) | |
724 | { | |
27b207fd WD |
725 | unsigned long stop; |
726 | struct rtc_time newtm; | |
77ddac94 | 727 | char *s; |
33149b88 | 728 | mem_test_reloc(); |
3e38691e | 729 | /* write correct LED configuration */ |
63ff004c | 730 | if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) { |
858b1a64 WD |
731 | printf ("Error writing to the PHY\n"); |
732 | } | |
3e38691e WD |
733 | /* since LED/CFG2 is not connected on the -2, |
734 | * write to correct capability information */ | |
63ff004c | 735 | if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) { |
3e38691e WD |
736 | printf ("Error writing to the PHY\n"); |
737 | } | |
858b1a64 | 738 | print_mip405_rev (); |
28c34504 | 739 | stdio_print_current_devices (); |
858b1a64 | 740 | check_env (); |
27b207fd WD |
741 | /* check if RTC time is valid */ |
742 | stop=get_timer(start); | |
743 | while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */ | |
744 | udelay(1000); | |
745 | stop=get_timer(start); | |
746 | } | |
747 | rtc_get (&newtm); | |
748 | if(tm.tm_sec==newtm.tm_sec) { | |
749 | s=getenv("defaultdate"); | |
750 | if(!s) | |
751 | mk_date ("010112001970", &newtm); | |
752 | else | |
753 | if(mk_date (s, &newtm)!=0) { | |
754 | printf("RTC: Bad date format in defaultdate\n"); | |
755 | return 0; | |
756 | } | |
757 | rtc_reset (); | |
758 | rtc_set(&newtm); | |
759 | } | |
858b1a64 WD |
760 | return 0; |
761 | } | |
762 | ||
763 | /*************************************************************************** | |
764 | * some helping routines | |
765 | */ | |
766 | ||
767 | int overwrite_console (void) | |
768 | { | |
769 | return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */ | |
770 | } | |
771 | ||
772 | ||
773 | /************************************************************************ | |
774 | * Print MIP405 Info | |
775 | ************************************************************************/ | |
776 | void print_mip405_info (void) | |
777 | { | |
778 | unsigned char part, vers, cfg, irq_reg, com_mode, ext; | |
779 | ||
780 | part = in8 (PLD_PART_REG); | |
781 | vers = in8 (PLD_VERS_REG); | |
782 | cfg = in8 (PLD_BOARD_CFG_REG); | |
783 | irq_reg = in8 (PLD_IRQ_REG); | |
784 | com_mode = in8 (PLD_COM_MODE_REG); | |
785 | ext = in8 (PLD_EXT_CONF_REG); | |
786 | ||
f3e0de60 | 787 | printf ("PLD Part %d version %d\n", part & 0x7F, vers); |
858b1a64 WD |
788 | printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A'); |
789 | printf ("Population Options %d %d %d %d\n", (cfg) & 0x1, | |
790 | (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1); | |
791 | printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off"); | |
792 | printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3); | |
f3e0de60 | 793 | #if !defined(CONFIG_MIP405T) |
858b1a64 WD |
794 | printf ("User Config Switch %d %d %d %d %d %d %d %d\n", |
795 | (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, | |
796 | (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, | |
797 | (ext >> 6) & 0x1, (ext >> 7) & 0x1); | |
798 | printf ("SER1 uses handshakes %s\n", | |
799 | (ext & 0x80) ? "DTR/DSR" : "RTS/CTS"); | |
f3e0de60 | 800 | #else |
27b207fd | 801 | printf ("User Config Switch %d %d %d %d %d %d %d %d\n", |
f3e0de60 WD |
802 | (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, |
803 | (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, | |
27b207fd | 804 | (ext >> 6) & 0x1,(ext >> 7) & 0x1); |
f3e0de60 | 805 | #endif |
858b1a64 WD |
806 | printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted"); |
807 | printf ("IRQs:\n"); | |
808 | printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active"); | |
f3e0de60 | 809 | #if !defined(CONFIG_MIP405T) |
858b1a64 WD |
810 | printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active"); |
811 | printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active"); | |
f3e0de60 | 812 | #endif |
858b1a64 WD |
813 | printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active"); |
814 | printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); | |
815 | printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); | |
816 | } |