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Commit | Line | Data |
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46263f2d | 1 | /* |
1b387ef5 | 2 | * SPDX-License-Identifier: GPL-2.0 IBM-pibs |
46263f2d | 3 | */ |
b573bf1d WD |
4 | /*----------------------------------------------------------------------------- |
5 | * Function: ext_bus_cntlr_init | |
6 | * Description: Initializes the External Bus Controller for the external | |
7 | * peripherals. IMPORTANT: For pass1 this code must run from | |
8 | * cache since you can not reliably change a peripheral banks | |
9 | * timing register (pbxap) while running code from that bank. | |
10 | * For ex., since we are running from ROM on bank 0, we can NOT | |
11 | * execute the code that modifies bank 0 timings from ROM, so | |
12 | * we run it from cache. | |
13 | * Bank 0 - Flash or Multi Purpose Socket | |
14 | * Bank 1 - Multi Purpose Socket or Flash | |
15 | * Bank 2 - not used | |
16 | * Bank 3 - not used | |
17 | * Bank 4 - not used | |
18 | * Bank 5 - not used | |
19 | * Bank 6 - used to switch on the 12V for the Multipurpose socket | |
20 | * Bank 7 - Config Register | |
21 | *-----------------------------------------------------------------------------*/ | |
b573bf1d | 22 | |
7205e407 | 23 | #include <configs/PIP405.h> |
b573bf1d WD |
24 | #include <ppc_asm.tmpl> |
25 | #include <ppc_defs.h> | |
26 | ||
27 | #include <asm/cache.h> | |
28 | #include <asm/mmu.h> | |
afabb498 | 29 | #include <asm/ppc4xx.h> |
7205e407 | 30 | #include "pip405.h" |
b573bf1d | 31 | |
7205e407 WD |
32 | .globl ext_bus_cntlr_init |
33 | ext_bus_cntlr_init: | |
34 | mflr r4 /* save link register */ | |
d1c3b275 | 35 | mfdcr r3,CPC0_PSR /* get strapping reg */ |
7205e407 WD |
36 | andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ |
37 | bnelr /* jump back if PCI boot */ | |
b573bf1d | 38 | |
b573bf1d WD |
39 | bl ..getAddr |
40 | ..getAddr: | |
41 | mflr r3 /* get address of ..getAddr */ | |
42 | mtlr r4 /* restore link register */ | |
43 | addi r4,0,14 /* set ctr to 14; used to prefetch */ | |
44 | mtctr r4 /* 14 cache lines to fit this function */ | |
8bde7f77 | 45 | /* in cache (gives us 8x14=112 instrctns) */ |
b573bf1d WD |
46 | ..ebcloop: |
47 | icbt r0,r3 /* prefetch cache line for addr in r3 */ | |
48 | addi r3,r3,32 /* move to next cache line */ | |
49 | bdnz ..ebcloop /* continue for 14 cache lines */ | |
50 | ||
51 | /*------------------------------------------------------------------- | |
52 | * Delay to ensure all accesses to ROM are complete before changing | |
53 | * bank 0 timings. | |
54 | *------------------------------------------------------------------- */ | |
55 | addis r3,0,0x0 | |
56 | ori r3,r3,0xA000 | |
57 | mtctr r3 | |
58 | ..spinlp: | |
59 | bdnz ..spinlp /* spin loop */ | |
60 | ||
61 | /*----------------------------------------------------------------------- | |
62 | * decide boot up mode | |
63 | *----------------------------------------------------------------------- */ | |
d1c3b275 SR |
64 | addi r4,0,PB0CR |
65 | mtdcr EBC0_CFGADDR,r4 | |
66 | mfdcr r4,EBC0_CFGDATA | |
b573bf1d WD |
67 | |
68 | andi. r0, r4, 0x2000 /* mask out irrelevant bits */ | |
7205e407 | 69 | beq 0f /* jump if 8 bit bus width */ |
b573bf1d WD |
70 | |
71 | /* setup 16 bit things | |
72 | *----------------------------------------------------------------------- | |
73 | * Memory Bank 0 (16 Bit Flash) initialization | |
74 | *---------------------------------------------------------------------- */ | |
75 | ||
d1c3b275 SR |
76 | addi r4,0,PB1AP |
77 | mtdcr EBC0_CFGADDR,r4 | |
7205e407 WD |
78 | addis r4,0,(FLASH_AP_B)@h |
79 | ori r4,r4,(FLASH_AP_B)@l | |
d1c3b275 | 80 | mtdcr EBC0_CFGDATA,r4 |
7205e407 | 81 | |
d1c3b275 SR |
82 | addi r4,0,PB0CR |
83 | mtdcr EBC0_CFGADDR,r4 | |
7205e407 WD |
84 | /* BS=0x010(4MB),BU=0x3(R/W), */ |
85 | addis r4,0,(FLASH_CR_B)@h | |
86 | ori r4,r4,(FLASH_CR_B)@l | |
d1c3b275 | 87 | mtdcr EBC0_CFGDATA,r4 |
b573bf1d WD |
88 | b 1f |
89 | ||
90 | 0: | |
7205e407 | 91 | /* 8Bit boot mode: */ |
b573bf1d | 92 | /*----------------------------------------------------------------------- |
7205e407 WD |
93 | * Memory Bank 0 Multi Purpose Socket initialization |
94 | *----------------------------------------------------------------------- */ | |
95 | /* 0x7F8FFE80 slowest boot */ | |
d1c3b275 SR |
96 | addi r4,0,PB1AP |
97 | mtdcr EBC0_CFGADDR,r4 | |
7205e407 WD |
98 | addis r4,0,(MPS_AP_B)@h |
99 | ori r4,r4,(MPS_AP_B)@l | |
d1c3b275 | 100 | mtdcr EBC0_CFGDATA,r4 |
7205e407 | 101 | |
d1c3b275 SR |
102 | addi r4,0,PB0CR |
103 | mtdcr EBC0_CFGADDR,r4 | |
7205e407 WD |
104 | /* BS=0x010(4MB),BU=0x3(R/W), */ |
105 | addis r4,0,(MPS_CR_B)@h | |
106 | ori r4,r4,(MPS_CR_B)@l | |
d1c3b275 | 107 | mtdcr EBC0_CFGDATA,r4 |
b573bf1d | 108 | |
b573bf1d | 109 | |
7205e407 | 110 | 1: |
b573bf1d | 111 | /*----------------------------------------------------------------------- |
7205e407 | 112 | * Memory Bank 2-3-4-5-6 (not used) initialization |
b573bf1d | 113 | *-----------------------------------------------------------------------*/ |
d1c3b275 SR |
114 | addi r4,0,PB1CR |
115 | mtdcr EBC0_CFGADDR,r4 | |
7205e407 WD |
116 | addis r4,0,0x0000 |
117 | ori r4,r4,0x0000 | |
d1c3b275 | 118 | mtdcr EBC0_CFGDATA,r4 |
b573bf1d | 119 | |
d1c3b275 SR |
120 | addi r4,0,PB2CR |
121 | mtdcr EBC0_CFGADDR,r4 | |
b573bf1d WD |
122 | addis r4,0,0x0000 |
123 | ori r4,r4,0x0000 | |
d1c3b275 | 124 | mtdcr EBC0_CFGDATA,r4 |
b573bf1d | 125 | |
d1c3b275 SR |
126 | addi r4,0,PB3CR |
127 | mtdcr EBC0_CFGADDR,r4 | |
b573bf1d WD |
128 | addis r4,0,0x0000 |
129 | ori r4,r4,0x0000 | |
d1c3b275 | 130 | mtdcr EBC0_CFGDATA,r4 |
b573bf1d | 131 | |
d1c3b275 SR |
132 | addi r4,0,PB4CR |
133 | mtdcr EBC0_CFGADDR,r4 | |
b573bf1d WD |
134 | addis r4,0,0x0000 |
135 | ori r4,r4,0x0000 | |
d1c3b275 | 136 | mtdcr EBC0_CFGDATA,r4 |
b573bf1d | 137 | |
d1c3b275 SR |
138 | addi r4,0,PB5CR |
139 | mtdcr EBC0_CFGADDR,r4 | |
b573bf1d WD |
140 | addis r4,0,0x0000 |
141 | ori r4,r4,0x0000 | |
d1c3b275 | 142 | mtdcr EBC0_CFGDATA,r4 |
b573bf1d | 143 | |
d1c3b275 SR |
144 | addi r4,0,PB6CR |
145 | mtdcr EBC0_CFGADDR,r4 | |
b573bf1d WD |
146 | addis r4,0,0x0000 |
147 | ori r4,r4,0x0000 | |
d1c3b275 | 148 | mtdcr EBC0_CFGDATA,r4 |
b573bf1d | 149 | |
d1c3b275 SR |
150 | addi r4,0,PB7CR |
151 | mtdcr EBC0_CFGADDR,r4 | |
7205e407 WD |
152 | addis r4,0,0x0000 |
153 | ori r4,r4,0x0000 | |
d1c3b275 | 154 | mtdcr EBC0_CFGDATA,r4 |
7205e407 | 155 | nop /* pass2 DCR errata #8 */ |
b573bf1d WD |
156 | blr |
157 | ||
7205e407 WD |
158 | #if defined(CONFIG_BOOT_PCI) |
159 | .section .bootpg,"ax" | |
160 | .globl _start_pci | |
161 | /******************************************* | |
162 | */ | |
163 | ||
164 | _start_pci: | |
165 | /* first handle errata #68 / PCI_18 */ | |
166 | iccci r0, r0 /* invalidate I-cache */ | |
167 | lis r31, 0 | |
168 | mticcr r31 /* ICCR = 0 (all uncachable) */ | |
169 | isync | |
170 | ||
171 | mfccr0 r28 /* set CCR0[24] = 1 */ | |
172 | ori r28, r28, 0x0080 | |
173 | mtccr0 r28 | |
174 | ||
175 | /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ | |
176 | lis r28, 0xEF40 | |
177 | addi r28, r28, 0x0004 | |
178 | stw r31, 0x0C(r28) /* clear PMM0PCIHA */ | |
179 | lis r29, 0xFFF8 /* open 512 kByte */ | |
180 | addi r29, r29, 0x0001/* and enable this region */ | |
181 | stwbrx r29, r0, r28 /* write PMM0MA */ | |
182 | ||
183 | lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ | |
184 | addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ | |
185 | ||
186 | lis r31, 0x8000 /* set en bit bus 0 */ | |
187 | ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ | |
188 | stwbrx r31, r0, r28 /* write it */ | |
189 | ||
190 | lwbrx r31, r0, r29 /* load XBCS register */ | |
191 | oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ | |
192 | stwbrx r31, r0, r29 /* write back XBCS register */ | |
193 | ||
194 | nop | |
195 | nop | |
196 | b _start /* normal start */ | |
197 | #endif |