[people/ms/u-boot.git] / board / mpl / vcma9 / lowlevel_init.S

/*
 * Memory Setup stuff - taken from blob memsetup.S
 *
 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
 *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
 *
 * Modified for MPL VCMA9 by
 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
 * (C) Copyright 2002, 2003, 2004, 2005
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */


#include <config.h>

/* register definitions */

#define PLD_BASE	0x28000000
#define MISC_REG	0x103
#define SDRAM_REG	0x106
#define BWSCON		0x48000000
#define CLKBASE		0x4C000000
#define LOCKTIME	0x0
#define MPLLCON		0x4
#define UPLLCON		0x8
#define GPIOBASE	0x56000000
#define GSTATUS1	0xB0
#define FASTCPU		0x02

/* some parameters for the board */
/* BWSCON */
#define DW8			(0x0)
#define DW16			(0x1)
#define DW32			(0x2)
#define WAIT			(0x1<<2)
#define UBLB			(0x1<<3)

/* BANKSIZE */
#define BURST_EN		(0x1<<7)

/* BANK0CON 200 */
#define B0_Tacs_200		0x0	/*  0clk  (or 0x1 1clk) */
#define B0_Tcos_200		0x1	/*  1clk  (or 0x2 2clk) */
#define B0_Tacc_200		0x5	/*  8clk  (or 0x6 10clk) */
#define B0_Tcoh_200		0x0	/*  0clk */
#define B0_Tcah_200		0x3	/*  4clk  (or0x01 1clk) */
#define B0_Tacp_200		0x0     /* page mode is not used */
#define B0_PMC_200		0x0	/* page mode disabled */

/* BANK0CON 250 */
#define B0_Tacs_250		0x0	/*  0clk  (or 0x1 1clk) */
#define B0_Tcos_250		0x1	/*  1clk  (or 0x2 2clk) */
#define B0_Tacc_250		0x5	/*  8clk  (or 0x7 14clk) */
#define B0_Tcoh_250		0x0	/*  0clk */
#define B0_Tcah_250		0x3	/*  4clk  (or 0x1 1clk) */
#define B0_Tacp_250		0x0     /* page mode is not used */
#define B0_PMC_250		0x0	/* page mode disabled */

/* BANK0CON 266 */
#define B0_Tacs_266		0x0	/*  0clk  (or 0x1 1clk) */
#define B0_Tcos_266		0x1	/*  1clk  (or 0x2 2clk) */
#define B0_Tacc_266		0x6	/*  10clk (or 0x7 14clk) */
#define B0_Tcoh_266		0x0	/*  0clk */
#define B0_Tcah_266		0x3	/*  4clk  (or 0x1 1clk) */
#define B0_Tacp_266		0x0     /* page mode is not used */
#define B0_PMC_266		0x0	/* page mode disabled */

/* BANK1CON 200 */
#define B1_Tacs_200		0x0	/*  0clk  (or 0x1 1clk) */
#define B1_Tcos_200		0x1	/*  1clk  (or 0x2 2clk) */
#define B1_Tacc_200		0x5	/*  8clk  (or 0x6 10clk) */
#define B1_Tcoh_200		0x0	/*  0clk */
#define B1_Tcah_200		0x3	/*  4clk  (or 0x1 1clk) */
#define B1_Tacp_200		0x0     /* page mode is not used */
#define B1_PMC_200		0x0	/* page mode disabled */

/* BANK1CON 250 */
#define B1_Tacs_250		0x0	/*  0clk  (or 0x1 1clk) */
#define B1_Tcos_250		0x1	/*  1clk  (or 0x2 2clk) */
#define B1_Tacc_250		0x5	/*  8clk  (or 0x7 14clk) */
#define B1_Tcoh_250		0x0	/*  0clk */
#define B1_Tcah_250		0x3	/*  4clk  (or 0x1 1clk) */
#define B1_Tacp_250		0x0     /* page mode is not used */
#define B1_PMC_250		0x0	/* page mode disabled */

/* BANK1CON 266 */
#define B1_Tacs_266		0x0	/*  0clk  (or 0x1 1clk) */
#define B1_Tcos_266		0x1	/*  1clk  (or 0x2 2clk) */
#define B1_Tacc_266		0x6	/*  10clk (or 0x7 14clk) */
#define B1_Tcoh_266		0x0	/*  0clk */
#define B1_Tcah_266		0x3	/*  4clk  (or 0x1 1clk) */
#define B1_Tacp_266		0x0     /* page mode is not used */
#define B1_PMC_266		0x0	/* page mode disabled */

/* BANK2CON 200 + 250 + 266 */
#define B2_Tacs			0x3	/*  4clk */
#define B2_Tcos			0x3	/*  4clk */
#define B2_Tacc			0x7     /* 14clk */
#define B2_Tcoh			0x3	/*  4clk */
#define B2_Tcah			0x3	/*  4clk */
#define B2_Tacp			0x0	/* page mode is not used */
#define B2_PMC			0x0     /* page mode disabled */

/* BANK3CON 200 + 250 + 266 */
#define B3_Tacs			0x3	/*  4clk */
#define B3_Tcos			0x3	/*  4clk */
#define B3_Tacc			0x7     /* 14clk */
#define B3_Tcoh			0x3	/*  4clk */
#define B3_Tcah			0x3	/*  4clk */
#define B3_Tacp			0x0	/* page mode is not used */
#define B3_PMC			0x0     /* page mode disabled */

/* BANK4CON 200 */
#define B4_Tacs_200		0x1	/*  1clk */
#define B4_Tcos_200		0x3	/*  4clk */
#define B4_Tacc_200		0x7	/* 14clk */
#define B4_Tcoh_200		0x3	/*  4clk */
#define B4_Tcah_200		0x2	/*  2clk */
#define B4_Tacp_200		0x0     /* page mode is not used */
#define B4_PMC_200		0x0	/* page mode disabled */

/* BANK4CON 250 */
#define B4_Tacs_250		0x1	/*  1clk */
#define B4_Tcos_250		0x3	/*  4clk */
#define B4_Tacc_250		0x7	/* 14clk */
#define B4_Tcoh_250		0x3	/*  4clk */
#define B4_Tcah_250		0x2	/*  2clk */
#define B4_Tacp_250		0x0     /* page mode is not used */
#define B4_PMC_250		0x0	/* page mode disabled */

/* BANK4CON 266 */
#define B4_Tacs_266		0x1	/*  1clk */
#define B4_Tcos_266		0x3	/*  4clk */
#define B4_Tacc_266		0x7	/* 14clk */
#define B4_Tcoh_266		0x3	/*  4clk */
#define B4_Tcah_266		0x2	/*  2clk */
#define B4_Tacp_266		0x0     /* page mode is not used */
#define B4_PMC_266		0x0	/* page mode disabled */

/* BANK5CON 200 */
#define B5_Tacs_200		0x0	/*  0clk */
#define B5_Tcos_200		0x3	/*  4clk */
#define B5_Tacc_200		0x4	/*  6clk */
#define B5_Tcoh_200		0x3	/*  4clk */
#define B5_Tcah_200		0x1	/*  1clk */
#define B5_Tacp_200		0x0     /* page mode is not used */
#define B5_PMC_200		0x0	/* page mode disabled */

/* BANK5CON 250 */
#define B5_Tacs_250		0x0	/*  0clk */
#define B5_Tcos_250		0x3	/*  4clk */
#define B5_Tacc_250		0x5	/*  8clk */
#define B5_Tcoh_250		0x3	/*  4clk */
#define B5_Tcah_250		0x1	/*  1clk */
#define B5_Tacp_250		0x0     /* page mode is not used */
#define B5_PMC_250		0x0	/* page mode disabled */

/* BANK5CON 266 */
#define B5_Tacs_266		0x0	/*  0clk */
#define B5_Tcos_266		0x3	/*  4clk */
#define B5_Tacc_266		0x5	/*  8clk */
#define B5_Tcoh_266		0x3	/*  4clk */
#define B5_Tcah_266		0x1	/*  1clk */
#define B5_Tacp_266		0x0     /* page mode is not used */
#define B5_PMC_266		0x0	/* page mode disabled */

#define B6_MT			0x3	/* SDRAM */
#define B6_Trcd_200		0x0	/* 2clk */
#define B6_Trcd_250		0x1	/* 3clk */
#define B6_Trcd_266		0x1	/* 3clk */
#define B6_SCAN			0x2	/* 10bit */

#define B7_MT			0x3	/* SDRAM */
#define B7_Trcd_200		0x0	/* 2clk */
#define B7_Trcd_250		0x1	/* 3clk */
#define B7_Trcd_266		0x1	/* 3clk */
#define B7_SCAN			0x2	/* 10bit */

/* REFRESH parameter */
#define REFEN			0x1	/* Refresh enable */
#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
#define Trp_200			0x0	/* 2clk */
#define Trp_250			0x1	/* 3clk */
#define Trp_266			0x1	/* 3clk */
#define Tsrc_200		0x1	/* 5clk */
#define Tsrc_250		0x2	/* 6clk */
#define Tsrc_266		0x3	/* 7clk */

/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
#define REFCNT_200		489
/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
#define REFCNT_250		99
/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
#define REFCNT_266		0
/**************************************/

.globl lowlevel_init
lowlevel_init:
	/* use r0 to relocate DATA read/write to flash rather than memory ! */
	ldr	r0, =CONFIG_SYS_TEXT_BASE
	ldr	r13, =BWSCON

	/* enable minimal access to PLD */
	ldr	r1, [r13]			/* load default BWSCON */
	orr	r1, r1, #(DW8 + UBLB) << 20	/* set necessary CS attrs */
	str	r1, [r13]			/* set BWSCON */
	ldr	r1, =0x7FF0			/* select slowest timing */
	str	r1, [r13, #0x18]		/* set BANKCON5 */

	ldr	r1, =PLD_BASE
	ldr	r2, =SETUPDATA
	ldrb	r1, [r1, #MISC_REG]
	sub	r2, r2, r0
	tst	r1, #FASTCPU			/* FASTCPU available ? */
	addeq	r2, r2, #SETUPENTRY_SIZE

	/* memory control configuration */
	/* r2 = pointer into timing table */
	/* r13 = pointer to MEM controller regs (starting with BWSCON) */
	add     r3, r2, #CSDATA_OFFSET
	add     r4, r3, #CSDATAENTRY_SIZE
0:
	ldr     r1, [r3], #4
	str     r1, [r13], #4
	cmp     r3, r4
	bne     0b

	/* PLD access is now possible */
	/* r3 = SDRAMDATA */
	/* r13 = pointer to MEM controller regs */
	ldr	r1, =PLD_BASE
	mov	r4, #SDRAMENTRY_SIZE
	ldrb	r1, [r1, #SDRAM_REG]
	/* calculate start and end point */
	mla	r3, r4, r1, r3
	add     r4, r3, r4
0:
	ldr     r1, [r3], #4
	str     r1, [r13], #4
	cmp     r3, r4
	bne     0b

	/* setup MPLL registers */
	ldr	r1, =CLKBASE
	ldr	r4, =0xFFFFFF
	add	r3, r2, #4		/* r3 points to PLL values */
	str	r4, [r1, #LOCKTIME]
	ldmia	r3, {r4,r5}
	str	r5, [r1, #UPLLCON]	/* writing PLL register */
					/* !! order seems to be important !! */
	/* a little delay */
	ldr	r3, =0x4000
0:
	subs	r3, r3, #1
	bne	0b

	str	r4, [r1, #MPLLCON]	/* writing PLL register */
					/* !! order seems to be important !! */
	/* a little delay */
	ldr	r3, =0x4000
0:
	subs	r3, r3, #1
	bne	0b

	/* everything is fine now */
	mov	pc, lr

	.ltorg
/* the literal pools origin */

#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
	((bws1) << 4) + \
	((bws2) << 8) + \
	((bws3) << 12) + \
	((bws4) << 16) + \
	((bws5) << 20) + \
	((bws6) << 24) + \
	((bws7) << 28)

#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
	((tacs) << 13) + \
	((tcos) << 11) + \
	((tacc) << 8) + \
	((tcoh) << 6) + \
	((tcah) << 4) + \
	((tacp) << 2) + \
	(pmc)

#define MK_BANKCON_SDRAM(trcd, scan) \
	((0x03) << 15) + \
	((trcd) << 2) + \
	(scan)

#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
	((enable) << 23) + \
	((trefmd) << 22) + \
	((trp) << 20) + \
	((tsrc) << 18) + \
	(cnt)

SETUPDATA:
	.word 0x32410002
	/* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
	.word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
	/* PLL values for USB clock */
	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)

	/* timing for 250 MHz*/
0:
	.equiv CSDATA_OFFSET, (. - SETUPDATA)
	.word MK_BWSCON(DW16, \
			DW32, \
			DW32, \
			DW16 + WAIT + UBLB, \
			DW8 + UBLB, \
			DW32, \
			DW32)

	.word MK_BANKCON(B0_Tacs_250, \
			 B0_Tcos_250, \
			 B0_Tacc_250, \
			 B0_Tcoh_250, \
			 B0_Tcah_250, \
			 B0_Tacp_250, \
			 B0_PMC_250)

	.word MK_BANKCON(B1_Tacs_250, \
			 B1_Tcos_250, \
			 B1_Tacc_250, \
			 B1_Tcoh_250, \
			 B1_Tcah_250, \
			 B1_Tacp_250, \
			 B1_PMC_250)

	.word MK_BANKCON(B2_Tacs, \
			 B2_Tcos, \
			 B2_Tacc, \
			 B2_Tcoh, \
			 B2_Tcah, \
			 B2_Tacp, \
			 B2_PMC)

	.word MK_BANKCON(B3_Tacs, \
			 B3_Tcos, \
			 B3_Tacc, \
			 B3_Tcoh, \
			 B3_Tcah, \
			 B3_Tacp, \
			 B3_PMC)

	.word MK_BANKCON(B4_Tacs_250, \
			 B4_Tcos_250, \
			 B4_Tacc_250, \
			 B4_Tcoh_250, \
			 B4_Tcah_250, \
			 B4_Tacp_250, \
			 B4_PMC_250)

	.word MK_BANKCON(B5_Tacs_250, \
			 B5_Tcos_250, \
			 B5_Tacc_250, \
			 B5_Tcoh_250, \
			 B5_Tcah_250, \
			 B5_Tacp_250, \
			 B5_PMC_250)

	.equiv CSDATAENTRY_SIZE, (. - 0b)
	/* 4Mx8x4 */
0:
	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
	.word 0x32 + BURST_EN
	.word 0x30
	.word 0x30
	.equiv SDRAMENTRY_SIZE, (. - 0b)

	/* 8Mx8x4 */
	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
	.word 0x32 + BURST_EN
	.word 0x30
	.word 0x30

	/* 2Mx8x4 */
	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
	.word 0x32 + BURST_EN
	.word 0x30
	.word 0x30

	/* 4Mx8x2 */
	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
	.word 0x32 + BURST_EN
	.word 0x30
	.word 0x30

	.equiv SETUPENTRY_SIZE, (. - SETUPDATA)

	.word 0x32410000
	/* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
	.word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
	/* PLL values for USB clock */
	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)

	/* timing for 200 MHz and default*/
	.word MK_BWSCON(DW16, \
			DW32, \
			DW32, \
			DW16 + WAIT + UBLB, \
			DW8 + UBLB, \
			DW32, \
			DW32)

	.word MK_BANKCON(B0_Tacs_200, \
			 B0_Tcos_200, \
			 B0_Tacc_200, \
			 B0_Tcoh_200, \
			 B0_Tcah_200, \
			 B0_Tacp_200, \
			 B0_PMC_200)

	.word MK_BANKCON(B1_Tacs_200, \
			 B1_Tcos_200, \
			 B1_Tacc_200, \
			 B1_Tcoh_200, \
			 B1_Tcah_200, \
			 B1_Tacp_200, \
			 B1_PMC_200)

	.word MK_BANKCON(B2_Tacs, \
			 B2_Tcos, \
			 B2_Tacc, \
			 B2_Tcoh, \
			 B2_Tcah, \
			 B2_Tacp, \
			 B2_PMC)

	.word MK_BANKCON(B3_Tacs, \
			 B3_Tcos, \
			 B3_Tacc, \
			 B3_Tcoh, \
			 B3_Tcah, \
			 B3_Tacp, \
			 B3_PMC)

	.word MK_BANKCON(B4_Tacs_200, \
			 B4_Tcos_200, \
			 B4_Tacc_200, \
			 B4_Tcoh_200, \
			 B4_Tcah_200, \
			 B4_Tacp_200, \
			 B4_PMC_200)

	.word MK_BANKCON(B5_Tacs_200, \
			 B5_Tcos_200, \
			 B5_Tacc_200, \
			 B5_Tcoh_200, \
			 B5_Tcah_200, \
			 B5_Tacp_200, \
			 B5_PMC_200)

	/* 4Mx8x4 */
	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
	.word 0x32 + BURST_EN
	.word 0x30
	.word 0x30

	/* 8Mx8x4 */
	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
	.word 0x32 + BURST_EN
	.word 0x30
	.word 0x30

	/* 2Mx8x4 */
	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
	.word 0x32 + BURST_EN
	.word 0x30
	.word 0x30

	/* 4Mx8x2 */
	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
	.word 0x32 + BURST_EN
	.word 0x30
	.word 0x30

	.equiv SETUPDATA_SIZE, (. - SETUPDATA)
Commit	Line	Data
1cb8e980 WD	1	/*
	2	* Memory Setup stuff - taken from blob memsetup.S
	3	*
	4	* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
	5	* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
	6	*
f3108304	7	* Modified for MPL VCMA9 by
1cb8e980	8	* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
f3108304	9	* (C) Copyright 2002, 2003, 2004, 2005
1cb8e980	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
1cb8e980 WD	12	*/
	13
	14
1cb8e980	15	#include <config.h>
1cb8e980	16
f3108304	17	/* register definitions */
1cb8e980	18
f3108304 DMEA	19	#define PLD_BASE 0x28000000
	20	#define MISC_REG 0x103
	21	#define SDRAM_REG 0x106
531716e1	22	#define BWSCON 0x48000000
f3108304 DMEA	23	#define CLKBASE 0x4C000000
	24	#define LOCKTIME 0x0
	25	#define MPLLCON 0x4
	26	#define UPLLCON 0x8
	27	#define GPIOBASE 0x56000000
	28	#define GSTATUS1 0xB0
	29	#define FASTCPU 0x02
1cb8e980	30
f3108304	31	/* some parameters for the board */
1cb8e980	32	/* BWSCON */
53677ef1 WD	33	#define DW8 (0x0)
	34	#define DW16 (0x1)
	35	#define DW32 (0x2)
	36	#define WAIT (0x1<<2)
	37	#define UBLB (0x1<<3)
1cb8e980	38
531716e1 WD	39	/* BANKSIZE */
	40	#define BURST_EN (0x1<<7)
	41
f3108304 DMEA	42	/* BANK0CON 200 */
	43	#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
	44	#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
	45	#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
	46	#define B0_Tcoh_200 0x0 /* 0clk */
	47	#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */
	48	#define B0_Tacp_200 0x0 /* page mode is not used */
	49	#define B0_PMC_200 0x0 /* page mode disabled */
	50
	51	/* BANK0CON 250 */
	52	#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
	53	#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
	54	#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
	55	#define B0_Tcoh_250 0x0 /* 0clk */
	56	#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
	57	#define B0_Tacp_250 0x0 /* page mode is not used */
	58	#define B0_PMC_250 0x0 /* page mode disabled */
	59
	60	/* BANK0CON 266 */
	61	#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
	62	#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
	63	#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
	64	#define B0_Tcoh_266 0x0 /* 0clk */
	65	#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
	66	#define B0_Tacp_266 0x0 /* page mode is not used */
	67	#define B0_PMC_266 0x0 /* page mode disabled */
	68
	69	/* BANK1CON 200 */
	70	#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
	71	#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
	72	#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
	73	#define B1_Tcoh_200 0x0 /* 0clk */
	74	#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */
	75	#define B1_Tacp_200 0x0 /* page mode is not used */
	76	#define B1_PMC_200 0x0 /* page mode disabled */
	77
	78	/* BANK1CON 250 */
	79	#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
	80	#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
	81	#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
	82	#define B1_Tcoh_250 0x0 /* 0clk */
	83	#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
	84	#define B1_Tacp_250 0x0 /* page mode is not used */
	85	#define B1_PMC_250 0x0 /* page mode disabled */
	86
	87	/* BANK1CON 266 */
	88	#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
	89	#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
	90	#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
	91	#define B1_Tcoh_266 0x0 /* 0clk */
	92	#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
	93	#define B1_Tacp_266 0x0 /* page mode is not used */
	94	#define B1_PMC_266 0x0 /* page mode disabled */
53677ef1	95
f3108304	96	/* BANK2CON 200 + 250 + 266 */
53677ef1 WD	97	#define B2_Tacs 0x3 /* 4clk */
	98	#define B2_Tcos 0x3 /* 4clk */
	99	#define B2_Tacc 0x7 /* 14clk */
	100	#define B2_Tcoh 0x3 /* 4clk */
f3108304	101	#define B2_Tcah 0x3 /* 4clk */
53677ef1 WD	102	#define B2_Tacp 0x0 /* page mode is not used */
	103	#define B2_PMC 0x0 /* page mode disabled */
	104
f3108304	105	/* BANK3CON 200 + 250 + 266 */
53677ef1 WD	106	#define B3_Tacs 0x3 /* 4clk */
	107	#define B3_Tcos 0x3 /* 4clk */
	108	#define B3_Tacc 0x7 /* 14clk */
	109	#define B3_Tcoh 0x3 /* 4clk */
f3108304	110	#define B3_Tcah 0x3 /* 4clk */
53677ef1 WD	111	#define B3_Tacp 0x0 /* page mode is not used */
	112	#define B3_PMC 0x0 /* page mode disabled */
	113
f3108304 DMEA	114	/* BANK4CON 200 */
	115	#define B4_Tacs_200 0x1 /* 1clk */
	116	#define B4_Tcos_200 0x3 /* 4clk */
	117	#define B4_Tacc_200 0x7 /* 14clk */
	118	#define B4_Tcoh_200 0x3 /* 4clk */
	119	#define B4_Tcah_200 0x2 /* 2clk */
	120	#define B4_Tacp_200 0x0 /* page mode is not used */
	121	#define B4_PMC_200 0x0 /* page mode disabled */
	122
	123	/* BANK4CON 250 */
	124	#define B4_Tacs_250 0x1 /* 1clk */
	125	#define B4_Tcos_250 0x3 /* 4clk */
	126	#define B4_Tacc_250 0x7 /* 14clk */
	127	#define B4_Tcoh_250 0x3 /* 4clk */
	128	#define B4_Tcah_250 0x2 /* 2clk */
	129	#define B4_Tacp_250 0x0 /* page mode is not used */
	130	#define B4_PMC_250 0x0 /* page mode disabled */
	131
	132	/* BANK4CON 266 */
	133	#define B4_Tacs_266 0x1 /* 1clk */
	134	#define B4_Tcos_266 0x3 /* 4clk */
	135	#define B4_Tacc_266 0x7 /* 14clk */
	136	#define B4_Tcoh_266 0x3 /* 4clk */
	137	#define B4_Tcah_266 0x2 /* 2clk */
	138	#define B4_Tacp_266 0x0 /* page mode is not used */
	139	#define B4_PMC_266 0x0 /* page mode disabled */
	140
	141	/* BANK5CON 200 */
	142	#define B5_Tacs_200 0x0 /* 0clk */
	143	#define B5_Tcos_200 0x3 /* 4clk */
	144	#define B5_Tacc_200 0x4 /* 6clk */
	145	#define B5_Tcoh_200 0x3 /* 4clk */
	146	#define B5_Tcah_200 0x1 /* 1clk */
	147	#define B5_Tacp_200 0x0 /* page mode is not used */
	148	#define B5_PMC_200 0x0 /* page mode disabled */
	149
	150	/* BANK5CON 250 */
	151	#define B5_Tacs_250 0x0 /* 0clk */
	152	#define B5_Tcos_250 0x3 /* 4clk */
	153	#define B5_Tacc_250 0x5 /* 8clk */
	154	#define B5_Tcoh_250 0x3 /* 4clk */
	155	#define B5_Tcah_250 0x1 /* 1clk */
	156	#define B5_Tacp_250 0x0 /* page mode is not used */
	157	#define B5_PMC_250 0x0 /* page mode disabled */
	158
	159	/* BANK5CON 266 */
	160	#define B5_Tacs_266 0x0 /* 0clk */
	161	#define B5_Tcos_266 0x3 /* 4clk */
	162	#define B5_Tacc_266 0x5 /* 8clk */
	163	#define B5_Tcoh_266 0x3 /* 4clk */
	164	#define B5_Tcah_266 0x1 /* 1clk */
	165	#define B5_Tacp_266 0x0 /* page mode is not used */
	166	#define B5_PMC_266 0x0 /* page mode disabled */
53677ef1 WD	167
53677ef1 WD	168	#define B6_MT 0x3 /* SDRAM */
f3108304 DMEA	169	#define B6_Trcd_200 0x0 /* 2clk */
	170	#define B6_Trcd_250 0x1 /* 3clk */
	171	#define B6_Trcd_266 0x1 /* 3clk */
53677ef1 WD	172	#define B6_SCAN 0x2 /* 10bit */
	173
	174	#define B7_MT 0x3 /* SDRAM */
f3108304 DMEA	175	#define B7_Trcd_200 0x0 /* 2clk */
	176	#define B7_Trcd_250 0x1 /* 3clk */
	177	#define B7_Trcd_266 0x1 /* 3clk */
53677ef1	178	#define B7_SCAN 0x2 /* 10bit */
1cb8e980 WD	179
1cb8e980 WD	180	/* REFRESH parameter */
53677ef1 WD	181	#define REFEN 0x1 /* Refresh enable */
53677ef1 WD	182	#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
f3108304 DMEA	183	#define Trp_200 0x0 /* 2clk */
	184	#define Trp_250 0x1 /* 3clk */
	185	#define Trp_266 0x1 /* 3clk */
	186	#define Tsrc_200 0x1 /* 5clk */
	187	#define Tsrc_250 0x2 /* 6clk */
	188	#define Tsrc_266 0x3 /* 7clk */
	189
	190	/* period=15.6us, HCLK=100Mhz, (2048+1-15.6100) /
	191	#define REFCNT_200 489
	192	/* period=15.6us, HCLK=125Mhz, (2048+1-15.6125) /
	193	#define REFCNT_250 99
	194	/* period=15.6us, HCLK=133Mhz, (2048+1-15.6133) /
	195	#define REFCNT_266 0
1cb8e980 WD	196	/**************************************/
1cb8e980 WD	197
400558b5 WD	198	.globl lowlevel_init
400558b5 WD	199	lowlevel_init:
f3108304	200	/* use r0 to relocate DATA read/write to flash rather than memory ! */
b60eff31	201	ldr r0, =CONFIG_SYS_TEXT_BASE
f3108304 DMEA	202	ldr r13, =BWSCON
	203
	204	/* enable minimal access to PLD */
	205	ldr r1, [r13] /* load default BWSCON */
	206	orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */
	207	str r1, [r13] /* set BWSCON */
	208	ldr r1, =0x7FF0 /* select slowest timing */
	209	str r1, [r13, #0x18] /* set BANKCON5 */
	210
	211	ldr r1, =PLD_BASE
	212	ldr r2, =SETUPDATA
	213	ldrb r1, [r1, #MISC_REG]
	214	sub r2, r2, r0
	215	tst r1, #FASTCPU /* FASTCPU available ? */
	216	addeq r2, r2, #SETUPENTRY_SIZE
	217
1cb8e980	218	/* memory control configuration */
f3108304 DMEA	219	/* r2 = pointer into timing table */
	220	/* r13 = pointer to MEM controller regs (starting with BWSCON) */
	221	add r3, r2, #CSDATA_OFFSET
	222	add r4, r3, #CSDATAENTRY_SIZE
1cb8e980	223	0:
f3108304 DMEA	224	ldr r1, [r3], #4
	225	str r1, [r13], #4
	226	cmp r3, r4
1cb8e980 WD	227	bne 0b
1cb8e980 WD	228
531716e1	229	/* PLD access is now possible */
6275331d	230	/* r3 = SDRAMDATA */
f3108304 DMEA	231	/* r13 = pointer to MEM controller regs */
	232	ldr r1, =PLD_BASE
	233	mov r4, #SDRAMENTRY_SIZE
	234	ldrb r1, [r1, #SDRAM_REG]
531716e1	235	/* calculate start and end point */
f3108304 DMEA	236	mla r3, r4, r1, r3
f3108304 DMEA	237	add r4, r3, r4
531716e1	238	0:
f3108304 DMEA	239	ldr r1, [r3], #4
	240	str r1, [r13], #4
	241	cmp r3, r4
531716e1	242	bne 0b
42d1f039	243
f3108304 DMEA	244	/* setup MPLL registers */
	245	ldr r1, =CLKBASE
	246	ldr r4, =0xFFFFFF
	247	add r3, r2, #4 /* r3 points to PLL values */
	248	str r4, [r1, #LOCKTIME]
	249	ldmia r3, {r4,r5}
	250	str r5, [r1, #UPLLCON] /* writing PLL register */
	251	/* !! order seems to be important !! */
	252	/* a little delay */
	253	ldr r3, =0x4000
	254	0:
	255	subs r3, r3, #1
	256	bne 0b
	257
	258	str r4, [r1, #MPLLCON] /* writing PLL register */
	259	/* !! order seems to be important !! */
	260	/* a little delay */
	261	ldr r3, =0x4000
	262	0:
	263	subs r3, r3, #1
	264	bne 0b
	265
1cb8e980 WD	266	/* everything is fine now */
	267	mov pc, lr
	268
	269	.ltorg
	270	/* the literal pools origin */
	271
f3108304 DMEA	272	#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
	273	((bws1) << 4) + \
	274	((bws2) << 8) + \
	275	((bws3) << 12) + \
	276	((bws4) << 16) + \
	277	((bws5) << 20) + \
	278	((bws6) << 24) + \
	279	((bws7) << 28)
	280
	281	#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
	282	((tacs) << 13) + \
	283	((tcos) << 11) + \
	284	((tacc) << 8) + \
	285	((tcoh) << 6) + \
	286	((tcah) << 4) + \
	287	((tacp) << 2) + \
	288	(pmc)
	289
	290	#define MK_BANKCON_SDRAM(trcd, scan) \
	291	((0x03) << 15) + \
	292	((trcd) << 2) + \
	293	(scan)
	294
	295	#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
	296	((enable) << 23) + \
	297	((trefmd) << 22) + \
	298	((trp) << 20) + \
	299	((tsrc) << 18) + \
	300	(cnt)
	301
	302	SETUPDATA:
	303	.word 0x32410002
	304	/* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
	305	.word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
	306	/* PLL values for USB clock */
	307	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
	308
	309	/* timing for 250 MHz*/
	310	0:
	311	.equiv CSDATA_OFFSET, (. - SETUPDATA)
	312	.word MK_BWSCON(DW16, \
	313	DW32, \
	314	DW32, \
	315	DW16 + WAIT + UBLB, \
	316	DW8 + UBLB, \
	317	DW32, \
	318	DW32)
	319
	320	.word MK_BANKCON(B0_Tacs_250, \
	321	B0_Tcos_250, \
	322	B0_Tacc_250, \
	323	B0_Tcoh_250, \
	324	B0_Tcah_250, \
	325	B0_Tacp_250, \
	326	B0_PMC_250)
	327
	328	.word MK_BANKCON(B1_Tacs_250, \
	329	B1_Tcos_250, \
	330	B1_Tacc_250, \
	331	B1_Tcoh_250, \
	332	B1_Tcah_250, \
	333	B1_Tacp_250, \
	334	B1_PMC_250)
	335
336	.word MK_BANKCON(B2_Tacs, \
337	B2_Tcos, \
338	B2_Tacc, \
339	B2_Tcoh, \
340	B2_Tcah, \
341	B2_Tacp, \
342	B2_PMC)
343
344	.word MK_BANKCON(B3_Tacs, \
345	B3_Tcos, \
346	B3_Tacc, \
347	B3_Tcoh, \
348	B3_Tcah, \
349	B3_Tacp, \
350	B3_PMC)
351
352	.word MK_BANKCON(B4_Tacs_250, \
353	B4_Tcos_250, \
354	B4_Tacc_250, \
355	B4_Tcoh_250, \
356	B4_Tcah_250, \
357	B4_Tacp_250, \
358	B4_PMC_250)
359
360	.word MK_BANKCON(B5_Tacs_250, \
361	B5_Tcos_250, \
362	B5_Tacc_250, \
363	B5_Tcoh_250, \
364	B5_Tcah_250, \
365	B5_Tacp_250, \
366	B5_PMC_250)
367
368	.equiv CSDATAENTRY_SIZE, (. - 0b)
369	/* 4Mx8x4 */
370	0:
371	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
372	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
373	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
374	.word 0x32 + BURST_EN
375	.word 0x30
376	.word 0x30
377	.equiv SDRAMENTRY_SIZE, (. - 0b)
378
379	/* 8Mx8x4 */
380	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
381	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
382	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
383	.word 0x32 + BURST_EN
384	.word 0x30
385	.word 0x30
386
387	/* 2Mx8x4 */
388	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
389	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
390	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
391	.word 0x32 + BURST_EN
392	.word 0x30
393	.word 0x30
394
395	/* 4Mx8x2 */
396	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
397	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
398	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
399	.word 0x32 + BURST_EN
400	.word 0x30
401	.word 0x30
402
403	.equiv SETUPENTRY_SIZE, (. - SETUPDATA)
404
405	.word 0x32410000
406	/* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
407	.word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
408	/* PLL values for USB clock */
409	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
410
411	/* timing for 200 MHz and default*/
412	.word MK_BWSCON(DW16, \
413	DW32, \
414	DW32, \
415	DW16 + WAIT + UBLB, \
416	DW8 + UBLB, \
417	DW32, \
418	DW32)
419
420	.word MK_BANKCON(B0_Tacs_200, \
421	B0_Tcos_200, \
422	B0_Tacc_200, \
423	B0_Tcoh_200, \
424	B0_Tcah_200, \
425	B0_Tacp_200, \
426	B0_PMC_200)
427
428	.word MK_BANKCON(B1_Tacs_200, \
429	B1_Tcos_200, \
430	B1_Tacc_200, \
431	B1_Tcoh_200, \
432	B1_Tcah_200, \
433	B1_Tacp_200, \
434	B1_PMC_200)
435
436	.word MK_BANKCON(B2_Tacs, \
437	B2_Tcos, \
438	B2_Tacc, \
439	B2_Tcoh, \
440	B2_Tcah, \
441	B2_Tacp, \
442	B2_PMC)
443
444	.word MK_BANKCON(B3_Tacs, \
445	B3_Tcos, \
446	B3_Tacc, \
447	B3_Tcoh, \
448	B3_Tcah, \
449	B3_Tacp, \
450	B3_PMC)
451
452	.word MK_BANKCON(B4_Tacs_200, \
453	B4_Tcos_200, \
454	B4_Tacc_200, \
455	B4_Tcoh_200, \
456	B4_Tcah_200, \
457	B4_Tacp_200, \
458	B4_PMC_200)
459
460	.word MK_BANKCON(B5_Tacs_200, \
461	B5_Tcos_200, \
462	B5_Tacc_200, \
463	B5_Tcoh_200, \
464	B5_Tcah_200, \
465	B5_Tacp_200, \
466	B5_PMC_200)
467
468	/* 4Mx8x4 */
469	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
470	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
471	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
472	.word 0x32 + BURST_EN
473	.word 0x30
474	.word 0x30
475
476	/* 8Mx8x4 */
477	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
478	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
479	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
480	.word 0x32 + BURST_EN
481	.word 0x30
482	.word 0x30
483
484	/* 2Mx8x4 */
485	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
486	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
487	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
488	.word 0x32 + BURST_EN
489	.word 0x30
490	.word 0x30
491
492	/* 4Mx8x2 */
493	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
494	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
495	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
496	.word 0x32 + BURST_EN
497	.word 0x30
498	.word 0x30
499
500	.equiv SETUPDATA_SIZE, (. - SETUPDATA)