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6c0bbdcc NI |
1 | /* |
2 | * Copyright (C) 2007 | |
3 | * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
61fb15c5 | 4 | * |
6c0bbdcc NI |
5 | * Copyright (C) 2007 |
6 | * Kenati Technologies, Inc. | |
7 | * | |
8 | * board/ms7722se/lowlevel_init.S | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <config.h> | |
27 | #include <version.h> | |
28 | ||
29 | #include <asm/processor.h> | |
f7e78f3b | 30 | #include <asm/macro.h> |
6c0bbdcc NI |
31 | |
32 | /* | |
e4430779 JCPV |
33 | * Board specific low level init code, called _very_ early in the |
34 | * startup sequence. Relocation to SDRAM has not happened yet, no | |
35 | * stack is available, bss section has not been initialised, etc. | |
6c0bbdcc | 36 | * |
e4430779 | 37 | * (Note: As no stack is available, no subroutines can be called...). |
6c0bbdcc NI |
38 | */ |
39 | ||
40 | .global lowlevel_init | |
41 | ||
42 | .text | |
43 | .align 2 | |
44 | ||
45 | lowlevel_init: | |
46 | ||
f7e78f3b JCPV |
47 | /* |
48 | * Cache Control Register | |
49 | * Instruction Cache Invalidate | |
50 | */ | |
51 | write32 CCR_A, CCR_D | |
6c0bbdcc | 52 | |
f7e78f3b JCPV |
53 | /* |
54 | * Address of MMU Control Register | |
55 | * TI == TLB Invalidate bit | |
56 | */ | |
57 | write32 MMUCR_A, MMUCR_D | |
6c0bbdcc | 58 | |
b5d10a13 | 59 | /* Address of Power Control Register 0 */ |
f7e78f3b | 60 | write32 MSTPCR0_A, MSTPCR0_D |
6c0bbdcc | 61 | |
b5d10a13 | 62 | /* Address of Power Control Register 2 */ |
f7e78f3b | 63 | write32 MSTPCR2_A, MSTPCR2_D |
6c0bbdcc | 64 | |
f7e78f3b | 65 | write16 SBSCR_A, SBSCR_D |
6c0bbdcc | 66 | |
f7e78f3b | 67 | write16 PSCR_A, PSCR_D |
6c0bbdcc | 68 | |
b5d10a13 | 69 | /* 0xA4520004 (Watchdog Control / Status Register) */ |
f7e78f3b | 70 | ! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */ |
6c0bbdcc | 71 | |
b5d10a13 | 72 | /* 0xA4520000 (Watchdog Count Register) */ |
f7e78f3b | 73 | write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */ |
6c0bbdcc | 74 | |
b5d10a13 | 75 | /* 0xA4520004 (Watchdog Control / Status Register) */ |
f7e78f3b | 76 | write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */ |
6c0bbdcc | 77 | |
b5d10a13 | 78 | /* 0xA4150000 Frequency control register */ |
f7e78f3b | 79 | write32 FRQCR_A, FRQCR_D |
6c0bbdcc | 80 | |
f7e78f3b | 81 | write32 CCR_A, CCR_D_2 |
6c0bbdcc NI |
82 | |
83 | bsc_init: | |
84 | ||
f7e78f3b | 85 | write16 PSELA_A, PSELA_D |
6c0bbdcc | 86 | |
f7e78f3b | 87 | write16 DRVCR_A, DRVCR_D |
6c0bbdcc | 88 | |
f7e78f3b | 89 | write16 PCCR_A, PCCR_D |
6c0bbdcc | 90 | |
f7e78f3b | 91 | write16 PECR_A, PECR_D |
6c0bbdcc | 92 | |
f7e78f3b | 93 | write16 PJCR_A, PJCR_D |
6c0bbdcc | 94 | |
f7e78f3b | 95 | write16 PXCR_A, PXCR_D |
6c0bbdcc | 96 | |
f7e78f3b | 97 | write32 CMNCR_A, CMNCR_D |
6c0bbdcc | 98 | |
f7e78f3b | 99 | write32 CS0BCR_A, CS0BCR_D |
6c0bbdcc | 100 | |
f7e78f3b | 101 | write32 CS2BCR_A, CS2BCR_D |
6c0bbdcc | 102 | |
f7e78f3b | 103 | write32 CS4BCR_A, CS4BCR_D |
6c0bbdcc | 104 | |
f7e78f3b | 105 | write32 CS5ABCR_A, CS5ABCR_D |
6c0bbdcc | 106 | |
f7e78f3b | 107 | write32 CS5BBCR_A, CS5BBCR_D |
6c0bbdcc | 108 | |
f7e78f3b | 109 | write32 CS6ABCR_A, CS6ABCR_D |
6c0bbdcc | 110 | |
f7e78f3b | 111 | write32 CS0WCR_A, CS0WCR_D |
6c0bbdcc | 112 | |
f7e78f3b | 113 | write32 CS2WCR_A, CS2WCR_D |
6c0bbdcc | 114 | |
f7e78f3b | 115 | write32 CS4WCR_A, CS4WCR_D |
6c0bbdcc | 116 | |
f7e78f3b | 117 | write32 CS5AWCR_A, CS5AWCR_D |
6c0bbdcc | 118 | |
f7e78f3b | 119 | write32 CS5BWCR_A, CS5BWCR_D |
6c0bbdcc | 120 | |
f7e78f3b | 121 | write32 CS6AWCR_A, CS6AWCR_D |
6c0bbdcc NI |
122 | |
123 | ! SDRAM initialization | |
f7e78f3b | 124 | write32 SDCR_A, SDCR_D |
6c0bbdcc | 125 | |
f7e78f3b | 126 | write32 SDWCR_A, SDWCR_D |
6c0bbdcc | 127 | |
f7e78f3b | 128 | write32 SDPCR_A, SDPCR_D |
6c0bbdcc | 129 | |
f7e78f3b | 130 | write32 RTCOR_A, RTCOR_D |
6c0bbdcc | 131 | |
f7e78f3b | 132 | write32 RTCSR_A, RTCSR_D |
6c0bbdcc | 133 | |
c9935c99 | 134 | write8 SDMR3_A, SDMR3_D |
6c0bbdcc | 135 | |
e4430779 | 136 | ! BL bit off (init = ON) (?!?) |
6c0bbdcc NI |
137 | |
138 | stc sr, r0 ! BL bit off(init=ON) | |
139 | mov.l SR_MASK_D, r1 | |
140 | and r1, r0 | |
141 | ldc r0, sr | |
142 | ||
143 | rts | |
144 | mov #0, r0 | |
145 | ||
6c0bbdcc NI |
146 | .align 2 |
147 | ||
61fb15c5 | 148 | CCR_A: .long CCR |
6c0bbdcc NI |
149 | MMUCR_A: .long MMUCR |
150 | MSTPCR0_A: .long MSTPCR0 | |
151 | MSTPCR2_A: .long MSTPCR2 | |
152 | SBSCR_A: .long SBSCR | |
153 | PSCR_A: .long PSCR | |
154 | RWTCSR_A: .long RWTCSR | |
155 | RWTCNT_A: .long RWTCNT | |
156 | FRQCR_A: .long FRQCR | |
157 | ||
158 | CCR_D: .long 0x00000800 | |
159 | CCR_D_2: .long 0x00000103 | |
160 | MMUCR_D: .long 0x00000004 | |
161 | MSTPCR0_D: .long 0x00001001 | |
162 | MSTPCR2_D: .long 0xffffffff | |
163 | FRQCR_D: .long 0x07022538 | |
164 | ||
e4430779 JCPV |
165 | PSELA_A: .long 0xa405014E |
166 | PSELA_D: .word 0x0A10 | |
61fb15c5 | 167 | .align 2 |
6c0bbdcc | 168 | |
e4430779 JCPV |
169 | DRVCR_A: .long 0xa405018A |
170 | DRVCR_D: .word 0x0554 | |
6c0bbdcc NI |
171 | .align 2 |
172 | ||
e4430779 JCPV |
173 | PCCR_A: .long 0xa4050104 |
174 | PCCR_D: .word 0x8800 | |
6c0bbdcc NI |
175 | .align 2 |
176 | ||
e4430779 JCPV |
177 | PECR_A: .long 0xa4050108 |
178 | PECR_D: .word 0x0000 | |
6c0bbdcc NI |
179 | .align 2 |
180 | ||
e4430779 JCPV |
181 | PJCR_A: .long 0xa4050110 |
182 | PJCR_D: .word 0x1000 | |
6c0bbdcc NI |
183 | .align 2 |
184 | ||
e4430779 JCPV |
185 | PXCR_A: .long 0xa4050148 |
186 | PXCR_D: .word 0x0AAA | |
6c0bbdcc NI |
187 | .align 2 |
188 | ||
189 | CMNCR_A: .long CMNCR | |
190 | CMNCR_D: .long 0x00000013 | |
191 | CS0BCR_A: .long CS0BCR ! Flash bank 1 | |
192 | CS0BCR_D: .long 0x24920400 | |
193 | CS2BCR_A: .long CS2BCR ! SRAM | |
194 | CS2BCR_D: .long 0x24920400 | |
195 | CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot | |
196 | CS4BCR_D: .long 0x24920400 | |
197 | CS5ABCR_A: .long CS5ABCR ! Ext slot | |
198 | CS5ABCR_D: .long 0x24920400 | |
199 | CS5BBCR_A: .long CS5BBCR ! USB controller | |
200 | CS5BBCR_D: .long 0x24920400 | |
201 | CS6ABCR_A: .long CS6ABCR ! Ethernet | |
202 | CS6ABCR_D: .long 0x24920400 | |
203 | ||
204 | CS0WCR_A: .long CS0WCR | |
205 | CS0WCR_D: .long 0x00000300 | |
206 | CS2WCR_A: .long CS2WCR | |
207 | CS2WCR_D: .long 0x00000300 | |
208 | CS4WCR_A: .long CS4WCR | |
209 | CS4WCR_D: .long 0x00000300 | |
210 | CS5AWCR_A: .long CS5AWCR | |
211 | CS5AWCR_D: .long 0x00000300 | |
212 | CS5BWCR_A: .long CS5BWCR | |
213 | CS5BWCR_D: .long 0x00000300 | |
214 | CS6AWCR_A: .long CS6AWCR | |
215 | CS6AWCR_D: .long 0x00000300 | |
216 | ||
217 | SDCR_A: .long SBSC_SDCR | |
218 | SDCR_D: .long 0x00020809 | |
219 | SDWCR_A: .long SBSC_SDWCR | |
220 | SDWCR_D: .long 0x00164d0d | |
221 | SDPCR_A: .long SBSC_SDPCR | |
222 | SDPCR_D: .long 0x00000087 | |
223 | RTCOR_A: .long SBSC_RTCOR | |
224 | RTCOR_D: .long 0xA55A0034 | |
225 | RTCSR_A: .long SBSC_RTCSR | |
226 | RTCSR_D: .long 0xA55A0010 | |
227 | SDMR3_A: .long 0xFE500180 | |
c9935c99 | 228 | SDMR3_D: .long 0x0 |
6c0bbdcc NI |
229 | |
230 | .align 1 | |
231 | ||
232 | SBSCR_D: .word 0x0040 | |
233 | PSCR_D: .word 0x0000 | |
234 | RWTCSR_D_1: .word 0xA507 | |
235 | RWTCSR_D_2: .word 0xA507 | |
236 | RWTCNT_D: .word 0x5A00 | |
b5d10a13 | 237 | .align 2 |
6c0bbdcc NI |
238 | |
239 | SR_MASK_D: .long 0xEFFFFF0F |