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Commit | Line | Data |
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69df3c4d | 1 | /* |
047375bf NI |
2 | modified from SH-IPL+g |
3 | Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting. | |
4 | ||
61fb15c5 WD |
5 | Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R |
6 | ||
047375bf NI |
7 | Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org> |
8 | ||
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
69df3c4d NI |
26 | */ |
27 | ||
28 | #include <config.h> | |
29 | #include <version.h> | |
30 | ||
31 | #include <asm/processor.h> | |
f7e78f3b | 32 | #include <asm/macro.h> |
69df3c4d | 33 | |
047375bf | 34 | #ifdef CONFIG_CPU_SH7751 |
e4430779 JCPV |
35 | #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ |
36 | #define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ | |
047375bf | 37 | #ifdef CONFIG_MARUBUN_PCCARD |
e4430779 JCPV |
38 | #define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 |
39 | A3:2 A2:15 A1:15 A0:6 A0B:7 */ | |
047375bf | 40 | #else /* CONFIG_MARUBUN_PCCARD */ |
e4430779 JCPV |
41 | #define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 |
42 | A3:2 A2:15 A1:15 A0:6 A0B:7 */ | |
047375bf | 43 | #endif /* CONFIG_MARUBUN_PCCARD */ |
e4430779 JCPV |
44 | #define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 |
45 | A2: 1-3 A1: 1-3 A0: 0-1 */ | |
46 | #define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ | |
47 | #define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ | |
48 | #define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ | |
49 | #define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ | |
047375bf | 50 | #else /* CONFIG_CPU_SH7751 */ |
e4430779 JCPV |
51 | #define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ |
52 | #define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ | |
53 | #define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 | |
54 | A3:2 A2:15 A1:15 A0:15 A0B:7 */ | |
55 | #define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 | |
56 | A2: 1-3 A1: 1-3 A0: 0-1 */ | |
57 | #define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ | |
58 | #define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ | |
59 | #define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ | |
60 | #define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ | |
047375bf | 61 | #endif /* CONFIG_CPU_SH7751 */ |
69df3c4d NI |
62 | |
63 | .global lowlevel_init | |
64 | .text | |
e4430779 | 65 | .align 2 |
69df3c4d NI |
66 | |
67 | lowlevel_init: | |
68 | ||
f7e78f3b | 69 | write32 CCR_A, CCR_D_DISABLE |
69df3c4d NI |
70 | |
71 | init_bsc: | |
f7e78f3b | 72 | write16 FRQCR_A, FRQCR_D |
69df3c4d | 73 | |
f7e78f3b | 74 | write32 BCR1_A, BCR1_D |
69df3c4d | 75 | |
f7e78f3b | 76 | write16 BCR2_A, BCR2_D |
69df3c4d | 77 | |
f7e78f3b | 78 | write32 WCR1_A, WCR1_D |
69df3c4d | 79 | |
f7e78f3b | 80 | write32 WCR2_A, WCR2_D |
69df3c4d | 81 | |
f7e78f3b | 82 | write32 WCR3_A, WCR3_D |
69df3c4d | 83 | |
f7e78f3b | 84 | write32 MCR_A, MCR_D1 |
69df3c4d | 85 | |
f7e78f3b | 86 | /* Set SDRAM mode */ |
c9935c99 | 87 | write8 SDMR3_A, SDMR3_D |
69df3c4d | 88 | |
61fb15c5 | 89 | ! Do you need PCMCIA setting? |
69df3c4d NI |
90 | ! If so, please add the lines here... |
91 | ||
f7e78f3b | 92 | write16 RTCNT_A, RTCNT_D |
69df3c4d | 93 | |
f7e78f3b | 94 | write16 RTCOR_A, RTCOR_D |
69df3c4d | 95 | |
f7e78f3b JCPV |
96 | write16 RTCSR_A, RTCSR_D |
97 | ||
98 | write16 RFCR_A, RFCR_D | |
69df3c4d | 99 | |
69df3c4d | 100 | /* Wait DRAM refresh 30 times */ |
e4430779 | 101 | mov #30, r3 |
69df3c4d | 102 | 1: |
e4430779 JCPV |
103 | mov.w @r1, r0 |
104 | extu.w r0, r2 | |
105 | cmp/hi r3, r2 | |
69df3c4d NI |
106 | bf 1b |
107 | ||
f7e78f3b | 108 | write32 MCR_A, MCR_D2 |
69df3c4d | 109 | |
f7e78f3b | 110 | /* Set SDRAM mode */ |
c9935c99 | 111 | write8 SDMR3_A, SDMR3_D |
69df3c4d NI |
112 | |
113 | rts | |
e4430779 | 114 | nop |
69df3c4d NI |
115 | |
116 | .align 2 | |
117 | ||
e4430779 JCPV |
118 | CCR_A: .long CCR |
119 | CCR_D_DISABLE: .long 0x0808 | |
69df3c4d NI |
120 | FRQCR_A: .long FRQCR |
121 | FRQCR_D: | |
047375bf | 122 | #ifdef CONFIG_CPU_TYPE_R |
33971937 | 123 | .word 0x0e1a /* 12:3:3 */ |
047375bf | 124 | #else /* CONFIG_CPU_TYPE_R */ |
69df3c4d | 125 | #ifdef CONFIG_GOOD_SESH4 |
33971937 | 126 | .word 0x00e13 /* 6:2:1 */ |
69df3c4d | 127 | #else |
33971937 | 128 | .word 0x00e23 /* 6:1:1 */ |
69df3c4d | 129 | #endif |
33971937 | 130 | .align 2 |
047375bf | 131 | #endif /* CONFIG_CPU_TYPE_R */ |
69df3c4d NI |
132 | |
133 | BCR1_A: .long BCR1 | |
134 | BCR1_D: .long 0x00000008 /* Area 3 SDRAM */ | |
135 | BCR2_A: .long BCR2 | |
136 | BCR2_D: .long BCR2_D_VALUE /* Bus width settings */ | |
137 | WCR1_A: .long WCR1 | |
138 | WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */ | |
139 | WCR2_A: .long WCR2 | |
140 | WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ | |
141 | WCR3_A: .long WCR3 | |
142 | WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ | |
61fb15c5 | 143 | RTCSR_A: .long RTCSR |
33971937 NI |
144 | RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ |
145 | .align 2 | |
69df3c4d | 146 | RTCNT_A: .long RTCNT |
33971937 NI |
147 | RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ |
148 | .align 2 | |
69df3c4d | 149 | RTCOR_A: .long RTCOR |
33971937 NI |
150 | RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ |
151 | .align 2 | |
69df3c4d | 152 | SDMR3_A: .long SDMR3_ADDRESS |
c9935c99 | 153 | SDMR3_D: .long 0x00 |
69df3c4d NI |
154 | MCR_A: .long MCR |
155 | MCR_D1: .long MCR_D1_VALUE | |
156 | MCR_D2: .long MCR_D2_VALUE | |
157 | RFCR_A: .long RFCR | |
33971937 NI |
158 | RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ |
159 | .align 2 |