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b4676a25 WD |
1 | /* |
2 | * GNU General Public License for more details. | |
3 | * | |
4 | * MATRIX Vision GmbH / June 2002-Nov 2003 | |
5 | * Andre Schwarz | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <mpc824x.h> | |
10 | #include <asm/io.h> | |
11 | #include <ns16550.h> | |
8ca0b3f9 | 12 | #include <netdev.h> |
b4676a25 WD |
13 | |
14 | #ifdef CONFIG_PCI | |
d4ca31c4 | 15 | #include <pci.h> |
b4676a25 WD |
16 | #endif |
17 | ||
d87080b7 WD |
18 | DECLARE_GLOBAL_DATA_PTR; |
19 | ||
d4ca31c4 | 20 | u32 get_BoardType (void); |
b4676a25 WD |
21 | |
22 | #define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \ | |
d4ca31c4 WD |
23 | | ((d&0x1f)<<11) \ |
24 | | ((f&0x7)<<7) \ | |
25 | | (r&0xfc) ) | |
b4676a25 | 26 | |
d4ca31c4 | 27 | int mv_pci_read (int bus, int dev, int func, int reg) |
b4676a25 | 28 | { |
d4ca31c4 WD |
29 | *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg); |
30 | asm ("sync"); | |
31 | return cpu_to_le32 (*(u32 *) (0xfee00cfc)); | |
b4676a25 | 32 | } |
d4ca31c4 WD |
33 | |
34 | u32 get_BoardType () | |
35 | { | |
36 | return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1); | |
b4676a25 WD |
37 | } |
38 | ||
d4ca31c4 | 39 | void init_2nd_DUART (void) |
b4676a25 | 40 | { |
6d0f6bcf JCPV |
41 | NS16550_t console = (NS16550_t) CONFIG_SYS_NS16550_COM2; |
42 | int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE; | |
d4ca31c4 WD |
43 | |
44 | *(u8 *) (0xfc004511) = 0x1; | |
45 | NS16550_init (console, clock_divisor); | |
b4676a25 | 46 | } |
d4ca31c4 | 47 | void hw_watchdog_reset (void) |
b4676a25 | 48 | { |
d4ca31c4 WD |
49 | if (get_BoardType () == 0) { |
50 | *(u32 *) (0xff000005) = 0; | |
51 | asm ("sync"); | |
b4676a25 WD |
52 | } |
53 | } | |
54 | int checkboard (void) | |
55 | { | |
d4ca31c4 WD |
56 | ulong busfreq = get_bus_freq (0); |
57 | char buf[32]; | |
58 | u32 BoardType = get_BoardType (); | |
b4676a25 WD |
59 | char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" }; |
60 | char *p; | |
61 | bd_t *bd = gd->bd; | |
62 | ||
d4ca31c4 WD |
63 | hw_watchdog_reset (); |
64 | ||
65 | printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION); | |
66 | printf (" Found %s running at %s MHz memory clock.\n", | |
67 | BoardName[BoardType], strmhz (buf, busfreq)); | |
b4676a25 | 68 | |
d4ca31c4 | 69 | init_2nd_DUART (); |
b4676a25 | 70 | |
d4ca31c4 WD |
71 | if ((p = getenv ("console_nr")) != NULL) { |
72 | unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; | |
b4676a25 | 73 | |
d4ca31c4 WD |
74 | bd->bi_baudrate &= ~3; |
75 | bd->bi_baudrate |= con_nr & 3; | |
b4676a25 WD |
76 | } |
77 | return 0; | |
78 | } | |
79 | ||
9973e3c6 | 80 | phys_size_t initdram (int board_type) |
b4676a25 | 81 | { |
c83bf6a2 WD |
82 | long size; |
83 | long new_bank0_end; | |
84 | long mear1; | |
85 | long emear1; | |
86 | ||
6d0f6bcf | 87 | size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); |
c83bf6a2 WD |
88 | |
89 | new_bank0_end = size - 1; | |
90 | mear1 = mpc824x_mpc107_getreg(MEAR1); | |
91 | emear1 = mpc824x_mpc107_getreg(EMEAR1); | |
92 | mear1 = (mear1 & 0xFFFFFF00) | | |
93 | ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); | |
94 | emear1 = (emear1 & 0xFFFFFF00) | | |
95 | ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); | |
96 | mpc824x_mpc107_setreg(MEAR1, mear1); | |
97 | mpc824x_mpc107_setreg(EMEAR1, emear1); | |
98 | ||
99 | return (size); | |
b4676a25 WD |
100 | } |
101 | ||
102 | /* ------------------------------------------------------------------------- */ | |
d4ca31c4 | 103 | u8 *dhcp_vendorex_prep (u8 * e) |
b4676a25 | 104 | { |
d4ca31c4 | 105 | char *ptr; |
b4676a25 WD |
106 | |
107 | /* DHCP vendor-class-identifier = 60 */ | |
d4ca31c4 WD |
108 | if ((ptr = getenv ("dhcp_vendor-class-identifier"))) { |
109 | *e++ = 60; | |
110 | *e++ = strlen (ptr); | |
111 | while (*ptr) | |
112 | *e++ = *ptr++; | |
113 | } | |
b4676a25 | 114 | /* my DHCP_CLIENT_IDENTIFIER = 61 */ |
d4ca31c4 WD |
115 | if ((ptr = getenv ("dhcp_client_id"))) { |
116 | *e++ = 61; | |
117 | *e++ = strlen (ptr); | |
118 | while (*ptr) | |
119 | *e++ = *ptr++; | |
120 | } | |
121 | return e; | |
b4676a25 | 122 | } |
d4ca31c4 WD |
123 | |
124 | u8 *dhcp_vendorex_proc (u8 * popt) | |
b4676a25 | 125 | { |
d4ca31c4 | 126 | return NULL; |
b4676a25 | 127 | } |
d4ca31c4 | 128 | |
b4676a25 WD |
129 | /* ------------------------------------------------------------------------- */ |
130 | ||
131 | /* | |
132 | * Initialize PCI Devices | |
133 | */ | |
134 | #ifdef CONFIG_PCI | |
d4ca31c4 | 135 | void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev) |
b4676a25 WD |
136 | { |
137 | u32 cnt; | |
d4ca31c4 WD |
138 | |
139 | printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev), | |
140 | PCI_FUNC (dev)); | |
141 | for (cnt = 0; cnt < 6; cnt++) | |
142 | pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt), | |
143 | 0x0); | |
144 | printf ("done\n"); | |
b4676a25 WD |
145 | } |
146 | ||
d4ca31c4 | 147 | void duart_setup (u32 base, u16 divisor) |
b4676a25 | 148 | { |
d4ca31c4 | 149 | printf ("duart setup ..."); |
6d0f6bcf JCPV |
150 | out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x80); |
151 | out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 0), divisor & 0xff); | |
152 | out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 1), divisor >> 8); | |
153 | out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x03); | |
154 | out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 4), 0x03); | |
155 | out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 2), 0x07); | |
d4ca31c4 | 156 | printf ("done\n"); |
b4676a25 WD |
157 | } |
158 | ||
d4ca31c4 WD |
159 | void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose, |
160 | pci_dev_t bridge, unsigned char irq) | |
b4676a25 WD |
161 | { |
162 | pci_dev_t d; | |
d4ca31c4 WD |
163 | unsigned char bus; |
164 | unsigned short vendor, class; | |
165 | ||
166 | pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus); | |
167 | for (d = PCI_BDF (bus, 0, 0); | |
168 | d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1, | |
169 | PCI_MAX_PCI_FUNCTIONS - 1); | |
170 | d += PCI_BDF (0, 0, 1)) { | |
171 | pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor); | |
172 | if (vendor != 0xffff && vendor != 0x0000) { | |
173 | pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE, | |
174 | &class); | |
175 | if (class == PCI_CLASS_BRIDGE_PCI) | |
176 | pci_mvblue_fixup_irq_behind_bridge (hose, d, | |
177 | irq); | |
b4676a25 | 178 | else |
d4ca31c4 WD |
179 | pci_hose_write_config_byte (hose, d, |
180 | PCI_INTERRUPT_LINE, | |
181 | irq); | |
b4676a25 WD |
182 | } |
183 | } | |
184 | } | |
185 | ||
186 | #define MV_MAX_PCI_BUSSES 3 | |
187 | #define SLOT0_IRQ 3 | |
188 | #define SLOT1_IRQ 4 | |
d4ca31c4 | 189 | void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev) |
b4676a25 | 190 | { |
d4ca31c4 WD |
191 | unsigned char line = 0xff; |
192 | unsigned short class; | |
b4676a25 | 193 | |
d4ca31c4 WD |
194 | if (PCI_BUS (dev) == 0) { |
195 | switch (PCI_DEV (dev)) { | |
196 | case 0xd: | |
197 | if (get_BoardType () == 0) { | |
b4676a25 WD |
198 | line = 1; |
199 | } else | |
200 | /* mvBL */ | |
d4ca31c4 WD |
201 | line = 2; |
202 | break; | |
203 | case 0xe: | |
b4676a25 WD |
204 | /* mvBB: IDE */ |
205 | line = 2; | |
d4ca31c4 | 206 | pci_hose_write_config_byte (hose, dev, 0x8a, 0x20); |
b4676a25 WD |
207 | break; |
208 | case 0xf: | |
209 | /* mvBB: Slot0 (Grabber) */ | |
d4ca31c4 WD |
210 | pci_hose_read_config_word (hose, dev, |
211 | PCI_CLASS_DEVICE, &class); | |
212 | if (class == PCI_CLASS_BRIDGE_PCI) { | |
213 | pci_mvblue_fixup_irq_behind_bridge (hose, dev, | |
214 | SLOT0_IRQ); | |
b4676a25 WD |
215 | line = 0xff; |
216 | } else | |
217 | line = SLOT0_IRQ; | |
218 | break; | |
219 | case 0x10: | |
220 | /* mvBB: Slot1 */ | |
d4ca31c4 WD |
221 | pci_hose_read_config_word (hose, dev, |
222 | PCI_CLASS_DEVICE, &class); | |
223 | if (class == PCI_CLASS_BRIDGE_PCI) { | |
224 | pci_mvblue_fixup_irq_behind_bridge (hose, dev, | |
225 | SLOT1_IRQ); | |
b4676a25 WD |
226 | line = 0xff; |
227 | } else | |
228 | line = SLOT1_IRQ; | |
229 | break; | |
d4ca31c4 WD |
230 | default: |
231 | printf ("***pci_scan: illegal dev = 0x%08x\n", | |
232 | PCI_DEV (dev)); | |
b4676a25 WD |
233 | line = 0xff; |
234 | break; | |
d4ca31c4 WD |
235 | } |
236 | pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, | |
237 | line); | |
b4676a25 WD |
238 | } |
239 | } | |
240 | ||
241 | struct pci_controller hose = { | |
d4ca31c4 | 242 | fixup_irq:pci_mvblue_fixup_irq |
b4676a25 WD |
243 | }; |
244 | ||
d4ca31c4 | 245 | void pci_init_board (void) |
b4676a25 | 246 | { |
d4ca31c4 | 247 | pci_mpc824x_init (&hose); |
b4676a25 | 248 | } |
8ca0b3f9 BW |
249 | |
250 | int board_eth_init(bd_t *bis) | |
251 | { | |
252 | return pci_eth_init(bis); | |
253 | } | |
b4676a25 | 254 | #endif |