[people/ms/u-boot.git] / board / mvblue / mvblue.c

/*
 * GNU General Public License for more details.
 *
 * MATRIX Vision GmbH / June 2002-Nov 2003
 * Andre Schwarz
 */

#include <common.h>
#include <mpc824x.h>
#include <asm/io.h>
#include <ns16550.h>

#ifdef CONFIG_PCI
	#include <pci.h>
#endif

u32 get_BoardType(void);

#define PCI_CONFIG(b,d,f,r)    cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
                                                      | ((d&0x1f)<<11) \
                                                      | ((f&0x7)<<7)   \
                                                      | (r&0xfc) )

int mv_pci_read( int bus, int dev, int func, int reg )
{
    *(u32*)(0xfec00cf8) = PCI_CONFIG(bus,dev,func,reg);
    asm("sync");
    return cpu_to_le32( *(u32*)(0xfee00cfc) );
}
u32 get_BoardType() {
	return ( mv_pci_read(0,0xe,0,0) == 0x06801095 ? 0 : 1 );
}

void init_2nd_DUART(void)
{
	NS16550_t console = (NS16550_t)CFG_NS16550_COM2;
	int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
	*(u8*)(0xfc004511) = 0x1;
	NS16550_init(console, clock_divisor);
}
void hw_watchdog_reset(void)
{
	if (get_BoardType() == 0 ) {
    	*(u32*)(0xff000005) = 0;
    	asm("sync");
	}
}
int checkboard (void)
{
	DECLARE_GLOBAL_DATA_PTR;
	ulong busfreq  = get_bus_freq(0);
	char  buf[32];
	u32   BoardType = get_BoardType();
	char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
	char *p;
	bd_t *bd = gd->bd;

	hw_watchdog_reset();

	printf("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
	printf("       Found %s running at %s MHz memory clock.\n", BoardName[BoardType], strmhz(buf, busfreq) );

	init_2nd_DUART();

    if ( (p = getenv("console_nr")) != NULL ) {
        unsigned long con_nr = simple_strtoul( p, NULL, 10) & 3;
        bd->bi_baudrate &= ~3;
        bd->bi_baudrate |= con_nr & 3;
	}
	return 0;
}

long int initdram (int board_type)
{
	int              i, cnt;
	volatile uchar * base= CFG_SDRAM_BASE;
	volatile ulong * addr;
	ulong            save[32];
	ulong            val, ret  = 0;

	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
		addr = (volatile ulong *)base + cnt;
		save[i++] = *addr;
		*addr = ~cnt;
	}

	addr = (volatile ulong *)base;
	save[i] = *addr;
	*addr = 0;

	if (*addr != 0) {
		*addr = save[i];
		goto Done;
	}

	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
		addr = (volatile ulong *)base + cnt;
		val = *addr;
		*addr = save[--i];
		if (val != ~cnt) {
			ulong new_bank0_end = cnt * sizeof(long) - 1;
			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
			mear1 =  (mear1  & 0xFFFFFF00) |
			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
			emear1 = (emear1 & 0xFFFFFF00) |
			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
			mpc824x_mpc107_setreg(MEAR1,  mear1);
			mpc824x_mpc107_setreg(EMEAR1, emear1);
			ret = cnt * sizeof(long);
			goto Done;
		}
	}

	ret = CFG_MAX_RAM_SIZE;
Done:
	return ret;
}

/* ------------------------------------------------------------------------- */
u8 *dhcp_vendorex_prep(u8 *e)
{
char *ptr;

	/* DHCP vendor-class-identifier = 60 */
    if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
        *e++ = 60;
        *e++ = strlen(ptr);
        while (*ptr)
            *e++ = *ptr++;
    }
	/* my DHCP_CLIENT_IDENTIFIER = 61 */
    if ((ptr = getenv("dhcp_client_id"))) {
        *e++ = 61;
        *e++ = strlen(ptr);
        while (*ptr)
            *e++ = *ptr++;
    }
    return e;
}
u8 *dhcp_vendorex_proc(u8 *popt)
{
    return NULL;
}
/* ------------------------------------------------------------------------- */

/*
 * Initialize PCI Devices
 */
#ifdef CONFIG_PCI
void pci_mvblue_clear_base( struct pci_controller *hose, pci_dev_t dev )
{
	u32 cnt;
	printf("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV(dev), PCI_FUNC(dev) );
    for( cnt = 0; cnt < 6; cnt++ )
    	pci_hose_write_config_dword( hose, dev, 0x10 + (4*cnt), 0x0 );
	printf("done\n");
}

void duart_setup( u32 base, u16 divisor )
{
	printf("duart setup ...");
	out_8( (u8*)( CFG_ISA_IO+base+3), 0x80);
    out_8( (u8*)( CFG_ISA_IO+base+0), divisor & 0xff);
    out_8( (u8*)( CFG_ISA_IO+base+1), divisor >> 8 );
    out_8( (u8*)( CFG_ISA_IO+base+3), 0x03);
    out_8( (u8*)( CFG_ISA_IO+base+4), 0x03);
    out_8( (u8*)( CFG_ISA_IO+base+2), 0x07);
	printf("done\n");
}

void pci_mvblue_fixup_irq_behind_bridge( struct pci_controller *hose, pci_dev_t bridge, unsigned char irq)
{
	pci_dev_t d;
	unsigned char 	bus;
	unsigned short 	vendor,
					class;

	pci_hose_read_config_byte( hose, bridge, PCI_SECONDARY_BUS, &bus );
	for (d =  PCI_BDF(bus,0,0);
         d <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
       	 d += PCI_BDF(0,0,1))
	{
        pci_hose_read_config_word(hose, d, PCI_VENDOR_ID, &vendor);
        if (vendor != 0xffff && vendor != 0x0000)
        {
			pci_hose_read_config_word( hose, d, PCI_CLASS_DEVICE, &class );
			if ( class == PCI_CLASS_BRIDGE_PCI )
				pci_mvblue_fixup_irq_behind_bridge( hose, d, irq );
			else
				pci_hose_write_config_byte( hose, d, PCI_INTERRUPT_LINE, irq );
		}
	}
}

#define MV_MAX_PCI_BUSSES	3
#define SLOT0_IRQ	3
#define SLOT1_IRQ	4
void pci_mvblue_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
    unsigned char 	line=0xff;
	unsigned short 	class;

	if( PCI_BUS(dev) == 0 ) {
	    switch(PCI_DEV(dev)) {
	    case 0xd:
			if ( get_BoardType() == 0 ) {
				line = 1;
			} else
				/* mvBL */
		        line = 2;
	        break;
	    case 0xe:
			/* mvBB: IDE */
			line = 2;
    		pci_hose_write_config_byte(hose, dev, 0x8a, 0x20 );
			break;
		case 0xf:
			/* mvBB: Slot0 (Grabber) */
			pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
			if ( class == PCI_CLASS_BRIDGE_PCI ) {
				pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT0_IRQ );
				line = 0xff;
			} else
				line = SLOT0_IRQ;
			break;
		case 0x10:
			/* mvBB: Slot1 */
			pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
			if ( class == PCI_CLASS_BRIDGE_PCI ) {
				pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT1_IRQ );
				line = 0xff;
			} else
				line = SLOT1_IRQ;
			break;
	    default:
			printf("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV(dev) );
			line = 0xff;
			break;
	    }
    	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line );
	}
}

struct pci_controller hose = {
	fixup_irq: pci_mvblue_fixup_irq
};

void pci_init_board(void)
{
	pci_mpc824x_init(&hose);
}
#endif
Commit	Line	Data
b4676a25 WD	1	/*
	2	* GNU General Public License for more details.
	3	*
	4	* MATRIX Vision GmbH / June 2002-Nov 2003
	5	* Andre Schwarz
	6	*/
	7
	8	#include <common.h>
	9	#include <mpc824x.h>
	10	#include <asm/io.h>
	11	#include <ns16550.h>
	12
	13	#ifdef CONFIG_PCI
	14	#include <pci.h>
	15	#endif
	16
	17	u32 get_BoardType(void);
	18
	19	#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 \| ((b&0xff)<<16) \
	20	\| ((d&0x1f)<<11) \
	21	\| ((f&0x7)<<7) \
	22	\| (r&0xfc) )
	23
	24	int mv_pci_read( int bus, int dev, int func, int reg )
	25	{
	26	(u32)(0xfec00cf8) = PCI_CONFIG(bus,dev,func,reg);
	27	asm("sync");
	28	return cpu_to_le32( (u32)(0xfee00cfc) );
	29	}
	30	u32 get_BoardType() {
	31	return ( mv_pci_read(0,0xe,0,0) == 0x06801095 ? 0 : 1 );
	32	}
	33
	34	void init_2nd_DUART(void)
	35	{
	36	NS16550_t console = (NS16550_t)CFG_NS16550_COM2;
	37	int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
	38	(u8)(0xfc004511) = 0x1;
	39	NS16550_init(console, clock_divisor);
	40	}
	41	void hw_watchdog_reset(void)
	42	{
	43	if (get_BoardType() == 0 ) {
	44	(u32)(0xff000005) = 0;
	45	asm("sync");
	46	}
	47	}
	48	int checkboard (void)
	49	{
	50	DECLARE_GLOBAL_DATA_PTR;
	51	ulong busfreq = get_bus_freq(0);
	52	char buf[32];
	53	u32 BoardType = get_BoardType();
	54	char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
	55	char *p;
	56	bd_t *bd = gd->bd;
	57
	58	hw_watchdog_reset();
	59
	60	printf("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
	61	printf(" Found %s running at %s MHz memory clock.\n", BoardName[BoardType], strmhz(buf, busfreq) );
	62
	63	init_2nd_DUART();
	64
65	if ( (p = getenv("console_nr")) != NULL ) {
66	unsigned long con_nr = simple_strtoul( p, NULL, 10) & 3;
67	bd->bi_baudrate &= ~3;
68	bd->bi_baudrate \|= con_nr & 3;
69	}
70	return 0;
71	}
72
73	long int initdram (int board_type)
74	{
75	int i, cnt;
76	volatile uchar * base= CFG_SDRAM_BASE;
77	volatile ulong * addr;
78	ulong save[32];
79	ulong val, ret = 0;
80
81	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
82	addr = (volatile ulong *)base + cnt;
83	save[i++] = *addr;
84	*addr = ~cnt;
85	}
86
87	addr = (volatile ulong *)base;
88	save[i] = *addr;
89	*addr = 0;
90
91	if (*addr != 0) {
92	*addr = save[i];
93	goto Done;
94	}
95
96	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
97	addr = (volatile ulong *)base + cnt;
98	val = *addr;
99	*addr = save[--i];
100	if (val != ~cnt) {
101	ulong new_bank0_end = cnt * sizeof(long) - 1;
102	ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
103	ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
104	mear1 = (mear1 & 0xFFFFFF00) \|
105	((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
106	emear1 = (emear1 & 0xFFFFFF00) \|
107	((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
108	mpc824x_mpc107_setreg(MEAR1, mear1);
109	mpc824x_mpc107_setreg(EMEAR1, emear1);
110	ret = cnt * sizeof(long);
111	goto Done;
112	}
113	}
114
115	ret = CFG_MAX_RAM_SIZE;
116	Done:
117	return ret;
118	}
119
120	/* ------------------------------------------------------------------------- */
121	u8 dhcp_vendorex_prep(u8 e)
122	{
123	char *ptr;
124
125	/* DHCP vendor-class-identifier = 60 */
126	if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
127	*e++ = 60;
128	*e++ = strlen(ptr);
129	while (*ptr)
130	e++ = ptr++;
131	}
132	/* my DHCP_CLIENT_IDENTIFIER = 61 */
133	if ((ptr = getenv("dhcp_client_id"))) {
134	*e++ = 61;
135	*e++ = strlen(ptr);
136	while (*ptr)
137	e++ = ptr++;
138	}
139	return e;
140	}
141	u8 dhcp_vendorex_proc(u8 popt)
142	{
143	return NULL;
144	}
145	/* ------------------------------------------------------------------------- */
146
147	/*
148	* Initialize PCI Devices
149	*/
150	#ifdef CONFIG_PCI
151	void pci_mvblue_clear_base( struct pci_controller *hose, pci_dev_t dev )
152	{
153	u32 cnt;
154	printf("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV(dev), PCI_FUNC(dev) );
155	for( cnt = 0; cnt < 6; cnt++ )
156	pci_hose_write_config_dword( hose, dev, 0x10 + (4*cnt), 0x0 );
157	printf("done\n");
158	}
159
160	void duart_setup( u32 base, u16 divisor )
161	{
162	printf("duart setup ...");
163	out_8( (u8*)( CFG_ISA_IO+base+3), 0x80);
164	out_8( (u8*)( CFG_ISA_IO+base+0), divisor & 0xff);
165	out_8( (u8*)( CFG_ISA_IO+base+1), divisor >> 8 );
166	out_8( (u8*)( CFG_ISA_IO+base+3), 0x03);
167	out_8( (u8*)( CFG_ISA_IO+base+4), 0x03);
168	out_8( (u8*)( CFG_ISA_IO+base+2), 0x07);
169	printf("done\n");
170	}
171
172	void pci_mvblue_fixup_irq_behind_bridge( struct pci_controller *hose, pci_dev_t bridge, unsigned char irq)
173	{
174	pci_dev_t d;
175	unsigned char bus;
176	unsigned short vendor,
177	class;
178
179	pci_hose_read_config_byte( hose, bridge, PCI_SECONDARY_BUS, &bus );
180	for (d = PCI_BDF(bus,0,0);
181	d < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
182	d += PCI_BDF(0,0,1))
183	{
184	pci_hose_read_config_word(hose, d, PCI_VENDOR_ID, &vendor);
185	if (vendor != 0xffff && vendor != 0x0000)
186	{
187	pci_hose_read_config_word( hose, d, PCI_CLASS_DEVICE, &class );
188	if ( class == PCI_CLASS_BRIDGE_PCI )
189	pci_mvblue_fixup_irq_behind_bridge( hose, d, irq );
190	else
191	pci_hose_write_config_byte( hose, d, PCI_INTERRUPT_LINE, irq );
192	}
193	}
194	}
195
196	#define MV_MAX_PCI_BUSSES 3
197	#define SLOT0_IRQ 3
198	#define SLOT1_IRQ 4
199	void pci_mvblue_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
200	{
201	unsigned char line=0xff;
202	unsigned short class;
203
204	if( PCI_BUS(dev) == 0 ) {
205	switch(PCI_DEV(dev)) {
206	case 0xd:
207	if ( get_BoardType() == 0 ) {
208	line = 1;
209	} else
210	/* mvBL */
211	line = 2;
212	break;
213	case 0xe:
214	/* mvBB: IDE */
215	line = 2;
216	pci_hose_write_config_byte(hose, dev, 0x8a, 0x20 );
217	break;
218	case 0xf:
219	/* mvBB: Slot0 (Grabber) */
220	pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
221	if ( class == PCI_CLASS_BRIDGE_PCI ) {
222	pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT0_IRQ );
223	line = 0xff;
224	} else
225	line = SLOT0_IRQ;
226	break;
227	case 0x10:
228	/* mvBB: Slot1 */
229	pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
230	if ( class == PCI_CLASS_BRIDGE_PCI ) {
231	pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT1_IRQ );
232	line = 0xff;
233	} else
234	line = SLOT1_IRQ;
235	break;
236	default:
237	printf("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV(dev) );
238	line = 0xff;
239	break;
240	}
241	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line );
242	}
243	}
244
245	struct pci_controller hose = {
246	fixup_irq: pci_mvblue_fixup_irq
247	};
248
249	void pci_init_board(void)
250	{
251	pci_mpc824x_init(&hose);
252	}
253	#endif